MT90840AP Zarlink, MT90840AP Datasheet - Page 57

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MT90840AP

Manufacturer Part Number
MT90840AP
Description
Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
Manufacturer
Zarlink
Datasheet

Specifications of MT90840AP

Package
84PLCC
Number Of Ports
16
Fabric Size
512 x 2430|512 x 512|2.373K x 2.373K
Switch Core
Non-Blocking
Port Speed
8.192|4.096|2.048 Mbps
Operating Supply Voltage
5 V

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MT90840AP
Manufacturer:
ZARLINK
Quantity:
1 831
Part Number:
MT90840AP
Manufacturer:
MITEL
Quantity:
20 000
AC Electrical Characteristics
(V
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
* High Impedance is measured by pulling to the appropriate rail with R
** Individual writes to Connection Memories will have Register Acknowledgment Delay. Burst writes to Connection Memories will have Read
Connection Memory Acknowledgment Delay.
10 CS setup from WR
11 Data setup from WR
12 Data hold after WR Inactive
13 RD/WR Inactive to ALE Falling Edge
14 Acknowledgment hold time
15 Data Delay on Reading Registers
16 Acknowledgment Delay
17 Acknowledgment Delay - Memories:
SS
1 ALE pulse width
2 Address setup from ALE falling
3 Address hold from ALE falling
4 RD Active after ALE falling
5 Data setup from DTA LOW on read
6 CS hold after RD/WR
7 CS setup from RD
8 Data hold after RD
9 WR delay after ALE falling
) unless otherwise stated.
Acknowledgment Delay
Reading Registers
Writing Registers
Reading TP Data Memory
Reading RP Data Memory
Reading TP Connection Memory
Reading RP Connection Memory
Writing TP Connection Memory**
Writing RP Connection Memory**
Characteristics
°
C and are for design aid only: not guaranteed and not subject to production testing.
- Intel/National- HPC Multiplexed Bus Mode -
t
Sym.
akd-mem
t
t
Zarlink Semiconductor Inc.
t
akd-wr
t
t
akd-rd
t
t
t
t
t
t
t
t
t
t
t
csrw
t
alwr
csw
dsw
dhw
alw
ads
adh
alrd
akh
ddr
csr
dhr
rdd
rst
MT90840
1 clock
cycle
t
t
57
Min.
244
122
244
akd-wr
akd-wr
L
10
15
10
15
15
10
23
5
5
0
0
0
0
0
0
, with timing corrected to cancel time taken to discharge C
2 clock
cycles
Typ.
488
366
488
3 clk cyc +
3 clk cyc +
Max.
1306
1062
t
t
817
akd-wr
774
akd-rd
22
30
20
47
68
73
85
32
41
Voltages are with respect to ground
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
and 30 pF on AD0-7.
C
C
C
C
C
C
C
C
C
1 to 5 C4 cycles +
register t
.5 to 4 C4 cycles +
register t
1 to 3 PCKT/R cycles
+ register t
1 to 3 C4 cycles +
register t
Up to 3 PCKT/R cyc.
+ register t
Up to 3 C4 cycles +
register t
Conditions/Notes
L
L
L
L
L
L
L
L
L
L
=150 pF on DTA,
=30 pF
=150 pF
=150 pF, R
=30 pF
=150 pF
=30 pF
=150 pF
=30 pF
=150 pF
Test
akd-rd
akd-rd
akd-rd
akd-wr
Data Sheet
akd-rd
akd-wr
L
.
L
=1kΩ*

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