MT90840AP Zarlink, MT90840AP Datasheet - Page 40

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Internal Memory Description
Phase Status Registers (PSD) - READ Only
Transmit Path Connection Memory High (TPCM High) - This is an 8-bit x 2430-position memory.
PSD10-0
OE/CTo0 Output Enable. Provides per channel tristate control on the parallel port side. It controls the MT90840 parallel output drivers to
PPBY
MC
CTo1-3
AB8-11
(every 250 µsec). PSD0 is the phase of the internal 4.096 MHz clock, PSD1-9 count the cycles of the 4.096 MHz within a
frame, and PSD10 toggles each frame (even/odd frame bit). The PSD bits enable the CPU to monitor the relative phases of the
Receive parallel port and the serial port. This is especially useful in TM1, where the PSD bits might be used by the CPU to
monitor a PLL control loop, since the elastic buffer in the Receive parallel port allows great variation in phase. These registers
should be read twice in succession, in case the CPU access occurs close to the sampling edge.
disable (tristate, when LOW) or enable (when HIGH) the transmission of data from the device. The contents of this bit will also
be clocked out on the CTo0 output pin at the parallel port rate.
Parallel Port Bypass Enable. Indicates that the parallel output channel is going to contain bypassed (PPBY=HIGH) data from
the Receive parallel port of the MT90840. The channels that are not bypassed (PPBY=LOW) can be used for switching of data
from the serial port side, or for message-mode data. The use of this bit is only allowed in Timing Modes 1 and 2. The PPBY bit
is overridden by MC set HIGH.
Message Channel. The message channel contents are programmed by the CPU into the TP Connection Memory Low. If MC=1
the contents of the corresponding location of TPCM Low are output on the corresponding channel at the Transmit parallel port.
If MC=LOW, the contents of the programmed location in TPCM Low act as an address for the Data Memory, and so determine
the source channel for this output channel. Depending on the timing mode selected, the source of the connection can be an input
channel from either serial (TM1, 2, or 3) or parallel (TM4) data ports. This bit overrides PPBY if both are set HIGH.
External Control Lines 1-3. These three bits are used by the CPU to program the three external control pins CTo1-3. Like
OE/CTo0, the contents of these lines will be transmitted to pins CTo1-3 at the parallel port rate. Note: CTo2 and CTo3 cannot
be used in Timing Mode 4.
Source Channel Address Bits 8-11. These bits are used along with bits AB0-7 in TPCM Low to select the source channel for
this output channel. In all timing modes except TM4, only bit AB8 is used, along with bits AB0-7 in TPCM Low, to select one
of 512 serial source channels from the serial port side to be transmitted on this output channel.
Phase Status Data 10-0. The PSD bits represent the phase status of the serial port, as sampled at every second PPFRi frame
PSD7
OE/
CTo0
7
7
7
0
PSD6
PPBY
0
6
6
6
PSD5
MC
0
5
5
5
PSD4
CTo1
0
4
4
4
Zarlink Semiconductor Inc.
CTo2/
AB11
PSD3
3
3
3
0
MT90840
PSD2
PSD10
CTo3/
AB10
40
2
2
2
PSD1
PSD9
AB9
1
1
1
PSD0
PSD8
AB8
0
0
0
(TX Path CM High)
Register Address 8 (Low Byte)
Register Address 9 (High 3-bits)
Data Sheet