MT90840AP Zarlink, MT90840AP Datasheet - Page 28

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

To cause the IRQ output signal or the indication bits to return to LOW again, the CPU can write any value to the
ALS Register (normally the Mask bits are re-written to clear the IRQ pin).
DTA Data Transfer Acknowledgment Pin
The DTA pin is driven LOW by internal logic, to indicate to the CPU that a data bus transfer is complete. When the
bus cycle ends, this pin drives HIGH and then switches to high-impedance. If a short, or a signal contention,
prevents the DTA pin from reaching a valid logic HIGH, it will continue to drive for approximately 15 nsec before
switching to high-impedance.
Accessing Internal Memories
The Data and Connection memories of the MT90840 are connected to the various TDM data ports, and
synchronized to the TDM clocks (PCKR, PCKT, and C4/8R1 or C4/8R2). Therefore all CPU accesses to the Data
and Connection memories are synchronized to, and dependent upon, the TDM clocks. The TDM clocks supplied to
the MT90840 must meet the requirements given in the AC Electrical Characteristics section for reliable operation of
both the data switch and the CPU port. Faulty clocks can result in data corruption at the TDM ports, or on CPU
accesses.
If there is no PCKR clock (PCKT in TM1), the CPU cannot access the Transmit Path Connection Memory. If there is
no C4/8 clock, the CPU cannot access the Transmit Path Data Memory, Receive Path Data Memory, or Receive
Path Connection Memory. If the PPFRi or F0 frame pulse is absent, but the other clocks are present, the MT90840
will free-run and allow normal CPU access. (In TM2 with the INTCLK bit asserted, or in TM3 or TM4, all clocks and
all CPU memory accesses are tied to the PCKR clock.)
CPU Memory Read Operation
To perform a read, the Control Register must first be written to specify the memory and page to be read. Then the
CPU can read the specified memory and page by latching an address into the MT90840, with address pin AD7
HIGH to indicate a memory access. When chip-select and read signals are asserted, data is transferred to the CPU
port on the next free TDM clock edge, and then the DTA pin is asserted to indicate that the CPU port data pins hold
valid read- data. Numerous reads within the same memory page can be performed without having to re-write the
Control Register. CPU reads of the Data and Connection memories must be multiplexed with the TDM port
accesses, resulting in the varying DTA response times given in the AC Electrical Characteristics section.
A7
0
0
0
0
0
0
0
0
0
0
0
A3
0
0
0
0
0
0
0
0
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
0
A1
1
0
0
1
1
0
0
1
0
0
1
Table 2 - MT90840 Register Address Mapping
A0
0
1
0
1
0
1
0
1
0
1
0
10
#
0
1
2
3
4
5
6
7
8
9
Zarlink Semiconductor Inc.
MT90840
Type
R/W
R/W
R/W
R/W
R/W
R/W
RO
RO
-
-
-
28
Phase Status (High 3 bits)
Phase Status (Low byte)
Test (leave 00hx)
Control Register
GPM Register
ALS Register
LOCATION
IMS Register
TIM Register
reserved
reserved
reserved
Reset Value
Data Sheet
(Hex)
XX
0X
0X
60
00
00
00
00