MT90840AP Zarlink, MT90840AP Datasheet - Page 42

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Applications
Distributed Isochronous Network
Low latency isochronous backbones provide for the deployment of systems that require cost effective
implementation, high bandwidth, predictable data transfer delays and direct synchronization with the wide area
network.
Some applications in Computer Telephony Integration (CTI) require a large amount of bandwidth to be transported
between multiple chassis within the same location, or between separate locations. The MT90840 is ideal for
implementing physically distributed transport and switching systems for multi-chassis or inter-shelf
communications.
The MT90840 bridges existing Zarlink ST-BUS components into a new networking environment where mixed data,
voice and video signals can be time-interchanged or multiplexed from serial PCM streams onto serial high-speed
time-division- multiplex (TDM) isochronous backbones operating at SONET rates such as 51 (STS-1) or 155 Mbps
(STS-3).
Receive Path Connection Memory High (RPCM High) - This is a 7-bit x 512-position memory.
Receive Path Connection Memory Low (RPCM Low) - This is an 8-bit x 512-position memory.
MC
DC
OE
AB8-11
AB0-7
Message Channel: The message channel contents are provided by the CPU in bits AB0-7 in the Rx Path Connection Memory
Low. If MC is HIGH, the contents of the corresponding location of RPCM Low are output on this serial port channel. If MC is
LOW, the contents of the corresponding location in RPCM Low act as an address for the Rx Path Data Memory and so
determine the source of the connection (input channels from the PDi0-7 port).
Direction Control: DC set HIGH indicates this channel is an output. DC set LOW indicates this channel is an input. The
operation of this bit is modified by the state of FDC in the IMS Register.
When FDC = LOW (2.048, 4.096 or 8.192 Mbps) the 512 DC bits (256 at 2.048) each define the direction of a pair of pins for
each channel. When DC is set LOW the associated channel on the STo pin becomes an input, and the corresponding channel on
the same-number STi pin is automatically used as the output for this time slot. When DC is set HIGH, STo is the output, and STi
is the input for this time slot (default).
When FDC = HIGH (2.048 Mbps), the 512 DC bits can be used to control the direction of each individual 64 kbps time slot
present on the 16 serial I/O lines on a non-symmetrical basis; i.e. all 512 channels can be configured as outputs or inputs or any
mixed combination. If DC is LOW, this serial port channel is defined as input. If DC is HIGH, this channel is defined as output.
Note that the CPU still has to set OE to enable the output buffers on each channel defined as an output.
Output Enable. Per-channel tristate control for each channel on the serial port side. If FDC is HIGH, the 512 OE bits enable the
output for each of the 512 ST channels, unless the channel is defined as an input by the DC bit. In 4.096 and 8.192 Mbps modes,
the OE bit enables the output buffer either on a STo pin, or an STi pin, as defined by the accompanying DC bit.
Source Channel Address. These 4 bits are used along with AB0-7 to select any of the 2430 parallel incoming channels from the
parallel port and determine the switch connection to the 512 possible destination channels on the serial port.
Source Channel Address. In switching mode (MC=LOW), these 8 bits are used along with AB8-11 to select one of the 2430
incoming channels from the parallel port. In message mode (MC=HIGH), these 8 bits are programmed by the CPU with the
message patterns desired on the corresponding serial output channel.
AB7
-
7
7
AB6
MC
6
6
AB5
DC
5
5
OE
AB4
4
4
Zarlink Semiconductor Inc.
AB11
AB3
3
3
MT90840
AB10
42
AB2
Used only in TM1, 2 &3.
2
2
Used only in TM1, 2, & 3.
AB9
AB1
1
1
AB8
AB0
0
0
(RX Path CM High)
(RX Path CM Low)
Data Sheet