MT90840AP Zarlink, MT90840AP Datasheet - Page 16

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Timing Mode 2 (TM2) - Ring Slave
Asynchronous Parallel Port With ST-BUS Clock Slave
Timing Mode 2 is used where the main TDM clock reference resides on the parallel port side of the system. (An
example is a node on a ring which is slaved to the ring clock.) Timing on the serial port is tightly tied (slaved) to the
receive parallel port, and the transmit parallel port is clocked by the receive parallel port clock. In TM2, the PCKT
input is not used. See Figure 6a for a connection example.
Note: the use of an external PLL is optional at 4.096 MHz (2.048 Mbps and 4.096 Mbps)
Source
8 kHz
8
8
8
8
RX Clock
8 kHz RX
RX Data
TX Clock
8 kHz TX
TX Data
8
TX Clock
8 kHz TX
Data TX
Data RX
8 kHz RX
8 kHz TX
Data TX
Figure 5b - TM1 Multiple-MT90840 Configuration
TX/RX Clock
Figure 6a - Timing Mode 2 Configuration
PCKR
PPFRi
PDi0-7
PCKT
PPFTo
PDo0-7
PCKR
PPFRi
PDi0-7
PCKT
PPFTi
PDo0-7
PCKR
PPFT
PDo0-7
PDi0-7
PPFRi
CPU
Zarlink Semiconductor Inc.
PFDI = 0
PFDI = 1
C4/8R1
C4/8R1
STo0-7
STo0-7
MT90840
MT90840
MT90840
STi0-7
STi0-7
MT90840
F0i
F0i
C4/8R1 & 2
16
PLL
8
8
4.096 MHz or
8.192 MHz
8 STi/o 0-7
8 STi/o 0-7
or 8.192 MHz
or 8.192 MHz
4.096
STi/o 0-7
4.096
STi/o 0-7
8 kHz
8 kHz
SPCKo
STo0-7
STi0-7
F0o
CPU
(8.192 MHz)
8
8
4.096 MHz
Components
8 kHz
ST-BUS
STi/o 0-7
STi/o 0-7
TX Clock
Source
8 kHz
PLL
Components
ST-BUS
Data Sheet