MT90840AP Zarlink, MT90840AP Datasheet - Page 33

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Test Data Registers
As specified in the IEEE 1149.1 Standard, the MT90840 JTAG interface contains two test data registers:
•
•
The MT90840 Boundary-Scan register contains 107 bits. The suffix (‘in’, ‘out’, or ‘en’) indicates the nature and
direction of the BSC. Bit 1 in Table 4 is the first bit clocked out. All tristate enable bits are asserted HIGH (i.e. a logic
1 enables the corresponding group of output/bidirectional pins). Note that clocking all zeros into the scan path
register will set all outputs to tristate (outputs disabled).
The Boundary Scan Register consists of a series of Boundary-Scan Cells arranged to form a scan path
around the boundary of the core logic of the MT90840.
The Bypass Register is a single stage shift-register that provides a one-bit path that minimizes the distance
for test data shifting from the MT90840’s TDI to its TDO.
1
2
3
4:11
12:14
15:22
23
24:27
28
29:31
32
33:35
36:53
54:56
57
58
59
60
61
Cells
Table 4 - Boundary-Scan Register
ppfri_in
pckt_in
pckr_in
pdi<0:7>_in
ppft_en, ppft_out, ppft_in
pdo<0:7>_out
pdo_en
cto<0:3>_out
c48r2_in
f0_en, f0_out, f0_in
c48r1_in
sti<7>_en, sti<7>_out,
sti<7>_in
sti<6>, sti<5>, ... sti<1>
sti<0>_en, sti<0>_out,
sti<0>_in
res_in
irq_en
irq_out
dta_out
cs_in
Zarlink Semiconductor Inc.
MT90840
Definition
33
first bit
out
enables
pdo<0:7>
outputs
always
enabled
tied
HIGH
internally
‘pseudo’
open-
drain
Note
Data Sheet