MT90840AP Zarlink, MT90840AP Datasheet - Page 4

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Pin Description
13-20
10,
26,
84
27
3
4
5
6
7
8
9
Pin #
27-31
50-54
76-80
57-64
100
1-4,
43
44
45
46
47
48
49
STi0-STi7
AS/ALE
DS/RD
Name
RES
DTA
IRQ
CS
NC
IC
Data Strobe/Read (Input). In Motorola multiplexed-bus mode this pin is DS, an
active high input which works with CS to enable read and write operation. In
Intel/National multiplexed-bus mode this pin is RD, an active low input which
enables a read-cycle and configures the data bus lines (AD0-AD7) as outputs.
Address Strobe / Address Latch Enable (Input). Falling edge is used to sample
address into the Address Latch circuit.
Chip Select (Input). Active low input enabling a microprocessor read or write of
control or status registers.
Data Acknowledgment (Active Low Output). Indicates that a data bus transfer is
complete. When the bus cycle ends, this pin drives HIGH and then tri-states,
allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is
required to hold a HIGH level when the pin is tri-stated. Note that CPU read/writes
from/to the Data and Connection memories occur on the serial or parallel port
clock edges, and DTA will not change state if the clock is halted.
Interrupt Request (Active High Output). Output indicates that the MT90840 has
detected an alarm condition. The indication of the specific condition can be read in
the ALS (Alarm Status) Register. The CPU should read ALS, identify the source for
the interrupt and then rewrite the mask bits to re-enable the IRQ signal.
RESET (Schmitt Input). Asynchronous device reset. A logic-high signal should be
applied during power-up to bring the MT90840 internal circuitry to a defined state.
Serial and parallel TDM outputs (STo0-7, STi0-7, and PDo0-7) are held in high-
impedance state after reset until programmed otherwise. This input must be held
low during normal operation.
Internal Connection. The user must connect this pin to V
low for the MT90840 to function normally, and to comply with IEEE 1149 (JTAG)
boundary scan requirements. This pin is pulled low internally when not driven.
No Connection.
Serial Inputs 0 to 7 (Bidirectional). Serial TDM data-streams at 2.048, 4.096 or
8.192 Mbps, with 32, 64 or 128 channels respectively per stream. For 2.048 and
4.096 Mbps applications, streams STi0-STi7 can be used, while for 8.192 Mbps,
only streams STi0-STi3 are used (512 channel limit). These eight bidirectional
lines can be programmed as inputs (default) or outputs on a per-channel basis.
Zarlink Semiconductor Inc.
MT90840
4
Description
SS
. This pin must remain
Data Sheet