MT90840AP Zarlink, MT90840AP Datasheet - Page 7

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Functional Description
The MT90840 Distributed Hyperchannel Switch is a large switching, multiplexing, and rate-adapting device. The
MT90840 bridges serial-bus telecom components, using the Zarlink ST-BUS or other industry-standard serial
buses, onto a higher speed “backbone”. Mixed data, voice and video signals can be time-interchanged or
multiplexed from serial Time Division Multiplexed (TDM) streams onto a high speed parallel bus. The parallel bus
can be used for interconnect, or an external framer can be connected to the parallel bus to access serial
isochronous backbones operating at up to 155 Mbps SONET rates (STS-3).
The MT90840 Distributed Hyperchannel Switch supports real-time multimedia applications through constant delay
switching. Multimedia data at N x 64 kbps rates uses N bytes (“time slots”, or “channels”) per 125 µsec frame. This
is also referred to as hyperchannel data. To ensure the integrity of data at N x 64 kbps rates, the network must
ensure that the N bytes in a given input frame remain together as a frame, and arrive at the destination as a frame.
The MT90840 supports this requirement by providing constant delay (frame integrity) which ensures that the
multiple time slots of associated data remain in the intended order.
Total TDM channel capacity of the MT90840 at maximum data rates is:
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•
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Pin Description (continued)
24,32,
43,53,
44,54,
66-73
76-83
64,74
2, 12,
25,33
63,75
1,11
512 serial input time slots,
512 serial output time slots,
2430 parallel input time slots, and
84
84
Pin #
15,25,
41,55,
68,74,
56,69,
17-24 STo7-STo0 Serial Output Streams 7 to 0 (Bidirectional). Serial TDM data-streams at 2.048,
32-39
90,10
5, 14,
26,42
75,91
100
40
0
R/W \ WR Read/Write \ Write (Input). In Motorola multiplexed-bus mode this input is
AD0-AD7
Name
V
V
SS
DD
4.096 or 8.192 Mbps, with 32, 64 or 128 channels respectively per stream. For
2.048 and 4.096 Mbps applications, streams STo0-STo7 can be used, while for
8.192 Mbps, only streams STo0-STo3 are used (512 channel limit). These eight
bidirectional lines can be programmed as inputs or outputs (default) on a per-
channel basis.
Multiplexed Address/Data Bus (Bidirectional). These I/O lines provide an 8-bit
interface to a microprocessor for control and monitoring of the MT90840. These
pins function as eight input address lines to the Address Latch circuit as well as
eight data I/O lines.
microprocessor access. In Intel/National multiplexed-bus mode this input is WR,
an active low signal which configures the data bus lines (AD0-AD7) as inputs
during a microprocessor write access.
Ground.
+5 Volt Power Supply.
R/W, which controls the direction of the data bus lines (AD0-AD7) during a
Zarlink Semiconductor Inc.
MT90840
7
Description
Data Sheet