MT90840AP Zarlink, MT90840AP Datasheet - Page 22

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Per-channel Direction Control on the Serial Port
The MT90840 provides the ability to use any nominal output serial channel as an input or as an output. The
direction of each output serial channel is controlled by the DC bit in the appropriate byte of the Receive Path
Connection Memory High (RPCM High). When DC is HIGH the matching channel is an output. The per-channel
direction control feature of the MT90840 can be activated in one two modes: balanced, or add/drop operation.
•
This mode is enabled when the FDC bit in the IMS Register is LOW. In this mode, each of the DC bits controls two
serial channels: the nominal output and the nominal input. If a channel on a nominal output serial stream (STo0-7)
is re-defined as an input, the same-number channel on the matching input stream (STi0-7) will be defined as an
output. For example, if channel 0 on STo7 is programmed as an input (DC=0), then channel 0 on STi7 is defined as
an output. Each DC-bit’s state controls the direction of a channel on the nominal output stream (DC is HIGH for
output), and inverse-sense controls a channel on the nominal input stream (DC is LOW for output). This is shown in
Figure 10.
•
This mode is enabled when the FDC bit in the IMS Register is HIGH. In Add/Drop mode all channels on all 16 serial
streams can be individually controlled, so that up to 512 channels can be either transmitted or received. As an
example, if all DC bit locations of RPCM High are set HIGH, all 512 channels on STo0-7 and STi0-7 will be
configured as outputs. If all DC bits are LOW, then all 512 channels will be configured as inputs. In Add/Drop mode
all 512 serial channels are copied into the Transmit Path Data Memory, as inputs, regardless of the DC or OE bits.
This has the effect of a “copy-back” of all serial outputs.
For more details on per-channel control functions for the serial and parallel data ports, see the TPCM High and
RPCM High bits definition in the Register Description section.
PDo7-0
Byte Timing
CTo0-3
Outputs
Note: For applications at 16.384 and 6.48 Mbyte/s, only 2048 and 810 positions are usable, in the TPCM.
PPFT
Balanced Operation (all serial data rates)
Add/Drop Operation (2.048 Mbps only)
0
O/P
1
TPCM High, CTn bit
Figure 10 - Balanced Per-Channel Serial Direction Control as Determined by DC Bit
2
address 2428
Channel 2428
3
STi0
. . . . .
Figure 9 - Parallel Port Control Outputs, CTo0-3
I/P
29
DC=0 for STo 0 channel 1
TPCM High, CTn bit
Channel 2429
address 2429
30
31
Output Frame Boundary Established by PPFT
Zarlink Semiconductor Inc.
MT90840
DC=1 for STo 0 channel 29
MT90840
22
TPCM High, CTn bit
0
address 0
Channel 0
1
I/P
2
3
. . . . .
TPCM High, CTn bit
STo0
address 1
Channel 1
O/P
29
Data Sheet
30
31