LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 11

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-5 shows the arrangement of the primary clock sources.
Figure 2-5. Clock Sources
Primary Clock Routing
The clock routing structure in LatticeSC devices consists of 12 Primary Clock lines per quadrant. The primary
clocks are generated from 64:1 MUXs located in each quadrant. Three of the inputs to each 64:1 MUX comes from
local routing, one is connected to GND and rest of the 60 inputs are from the primary clock sources. Figure 2-6
shows this clock routing.
Primary/
Edge Clock
PIOs
Edge Clock
PIOs
Primary/
Edge Clock
PIOs
• Two outputs per PLL
• Clock divider outputs
• Digital Clock Select (DCS) block outputs
• Three outputs per SERDES quad
DCS
DCS
PLL
DLL
DLL
DLL
DLL
DLL
DLL
PLL
PLL
PLL
Dividers
Clock
(3 per SERDES Channel)
SERDES
24
Edge
Clock
PIOs
Clock Dividers
Edge Clock
Primary/
PIOs
Primary Clock Sources
Clock
Edge
PIOs
DCS
DCS
8
2-7
4
Edge Clock
Primary/
DCS
DCS
PIOs
Clock Dividers
Edge
Clock
PIOs
Clock Dividers
(3 per SERDES Channel)
Edge Clock
SERDES
LatticeSC/M Family Data Sheet
Primary/
PIOs
24
Dividers
Clock
DLL
DLL
DLL
DLL
DLL
DLL
PLL
PLL
PLL
PLL
DCS
DCS
Architecture
Primary/
Edge Clock
PIOs
Edge Clock
PIOs
Primary/
Edge Clock
PIOs