LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 78

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Signal Descriptions (Cont.)
Lattice Semiconductor
D[n:0]
DP[m:0]
BUSYN/RCLK/SCK
MPI Interface (Dedicated pin)
MPI_IRQ_N
MPI Interface (User I/O if MPI is not used.)
MPI_CS0N MPI_CS1
MPI_CLK
MPI_TSIZ[1:0]
MPI_WR_N
MPI_BURST
MPI_BDIP
Signal Name
I/O
I/O
I/O
O
O
I
I
I
I
I
I
In parallel configuration modes, D[7:0] receives configuration data,
and each pin is pull-up enabled. For slave serial mode, D0 is the data
input.
D[7:3] is the output internal status for peripheral mode when RDN is
low.
D[7:0] is also the first byte of MPI data pins.
In MPI configuration mode, MPI selectable data bus width from 8 and
16-bit. Driven by a bus master in a write transaction. Driven by MPI in
a read transaction.
MPI selectable parity data bus width from 1, 2, and 3-bit DP[0] for
D[7:0], DP[1] for D[15:8], and DP[2] for D[23:16].
During configuration in peripheral mode, high on BUSYN indicates
another byte can be written to the FPGA. If a read operation is done
when the device is selected, the same status is also available on D[7]
in asynchronous peripheral mode.
During configuration in slave parallel mode, low on BUSYN inhibits the
external host from sending new data. The output is used by slave par-
allel and master serial modes only for decompression.
During configuration in master parallel and master byte modes, RCLK
is a read clock output signal to an external memory. The RCLK fre-
quency is the same as CCLK when used with uncompressed bit-
streams. RCLK will be 1/8 the frequency of CCLK when the bitstream
is compressed.
During configuration in SPI modes, SCK is generated by the device
and connected to the CLK input of the FLASH memory.
MPI Interrupt request active low signal is controlled by system bus
interrupt controller and may be sourced from any bus error or MPI con-
figuration error. It can be connected to one of MPC860 IRQ pins.
MPI chip select pins, active low on MPI_CS0N while active high on
MPI_CS1. Both have to be active during the whole transfer data
phase. During transfer address phase, both can be inactive so that the
decoding for them from address can be slow. If they are active during
address phase, one cycle can be saved for sync read.
This is the PowerPC bus clock. It can be a source of the clock for
embedded system bus. If MPI_CLK is used as system bus clock, MPI
will be set into sync mode by default. All of the operation on PowerPC
side of MPI are synchronized to the rising edge of this clock.
Driven by a bus master to indicate the data transfer size for the trans-
action. 01 for byte, 10 for half-word, and 00 for word.
Driven high indicates that a read access is in progress. Driven low
indicates that a write access is in process.
Driven active low indicates that a burst transfer is in progress. Driven
high indicates that the current transfer is not a burst.
Active low “Burst Data in Process” is driven by a PowerPC processor.
Asserted indicates that the second beat in front of the current one is
requested by the master. Negated before the burst transfer ends to
abort the burst data phase.
4-4
LatticeSC/M Family Data Sheet
Description
Pinout Information