LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 20

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-17. PIC Diagram
The A/B PIOs on the left and the right of the device can be paired to form a differentiated driver. The A/B and C/D
PIOs on all sides of the device can be paired to form differential receivers. Either A or C PIOs on all sides except
the one on top also provide a connection to an adaptive input logic capability that facilitates the implementation of
UPDATE
RUNAIL
ONEG0
ONEG1
ONEG2
ONEG3
OPOS0
OPOS1
OPOS2
OPOS3
INEG0
INEG1
INEG2
INEG3
IPOS0
IPOS1
IPOS2
IPOS3
GSRN
LOCK
ELSR
ECLK
INDD
INCK
INFF
CLK
LSR
CE
TD
*AIL only on A or C pads located on the left, right and bottom of the device.
HCLKOUT
LCLKOUT
Control
Muxes
HCLKIN
LCLKIN
LSRO
LSRO
CEO
GSR
PIO A
PIO D
PIO B
PIO C
Register Block
Register Block
Register Block
AIL elements*)
Update Block
(including
delay and
Tristate
Output
Input
POS Update
NEG Update
2-16
IOLT0
DO
DI
LatticeSC/M Family Data Sheet
DO
DI
PURESPEED
I/O Buffer
TO
PADA
PADD
PADB
PADC
"T"
“C”
“C”
“T”
Architecture