LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 71

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeSC/M sysCONFIG Port Timing
General Configuration Timing
t
t
t
t
f
sysCONFIG Master Parallel Configuration Mode
t
t
t
t
sysCONFIG SPI Port
t
t
t
t
t
f
t
t
sysCONFIG Master Serial Configuration Mode
t
t
f
f
t
sysCONFIG Master Parallel Configuration Mode
t
t
t
t
t
t
SMODE
HMODE
RW
PGW
ESB_CLK_FRQ
SMB
HMB
CLMB
CHMB
CFGX
CSSPI
SCK
SOCDO
CSPID
MAXSPI
SUSPI
HSPI
SMS
HMS
CMS
C_DIV
D
AVMP
SMP
HMP
CLMP
CHMP
DMP
Parameter
M[3:0] Setup Time to INITN High
M[3:0] Hold Time from INITN High
RESETN Pulse Width Low to Start Reconfiguration (1.2 V)
PROGRAMN Pulse Width Low to Start Reconfiguration (1.2 V)
System Bus ESB_CLK Frequency (No Wait States)
D[7:0] Setup Time to RCLK High
D[7:0] Hold Time to RCLK High
RCLK Low Time (Non-compressed Bitstreams)
RCLK Low Time (Compressed Bitstreams)
RCLK High Time
INITN High to CSCK Low
INITN High to CSSPIN Low
CSCK Low before CSSPIN Low
CSCK Low to Output Valid
CSSPIN Low to CSCK high Setup Time
Max CCLK Frequency - SPI Flash Fast Read Opcode (0x0B)
(SPIFASTN=0)
SOSPI/D0 Data Setup Time Before CSCK
SOSPI/D0 Data Hold Time After CSCK
Master Clock Frequency
Duty Cycle
DIN Setup Time
DIN Hold Time
CCLK Frequency (No Divider)
CCLK Frequency (Div 128)
CCLK to DOUT Delay
RCLK to Address Valid
D[7:0] Setup Time to RCLK High
D[7:0] Hold Time to RCLK High
RCLK Low Time (Non-compressed Bitstream)
RCLK Low Time (Compressed Bitstream)
RCLK High Time
CCLK to DOUT
Over Recommended Operating Conditions
Description
3-27
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
50 (or 100 at
50 (or 100 at
value - 30%
Selected
0.95V)
0.95V)
Min.
0.70
600
0.5
0.5
0.5
4.4
7.5
0.5
0.5
40
90
—
—
—
—
—
—
—
—
0
6
0
0
0
7
2
0
6
0
value + 30%
Selected
Max.
1.48
63.5
133
190
0.5
7.5
0.5
7.5
7.5
0.5
7.5
80
50
60
10
—
—
—
—
—
—
—
15
15
—
—
—
—
—
—
2
periods
periods
periods
periods
periods
CCLK
CCLK
CCLK
CCLK
CCLK
Units
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%