LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 35

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Single Ended Inputs: The SC devices support a number of different termination schemes for single ended inputs:
Figure 2-28 shows the single ended input schemes that are supported. The nominal values of the termination resis-
tors are shown in Table 2-9.
Figure 2-28. Input Termination Schemes
In many situations designers can chose whether to use Thevenin or parallel to V
approach has the benefit of not requiring a termination voltage to be applied to the device. The parallel to V
approach consumes less power.
VTT Termination Resources
Each I/O bank, except bank 1, has a number of V
sink or source current and the power supply they are connected to must be able to handle the relatively high currents
associated with the termination circuits. Note: V
On-chip parallel termination to V
not supported.
The V
V
DDRII/RLDRAMII Termination Support
The DDR II memory and RLDRAMII (in Bidirection Data mode) standards require that the on-chip termination to V
be turned on when a pin is an input and off when the pin is an output. The LatticeSC devices contain the required cir-
cuitry to support this behavior. For additional detail refer to technical information at the end of the data sheet.
TT
Parallel termination to
GND receiving end
Parallel termination to
V
Parallel termination to
to V
V
CCIO
TT
Termination Type
termination or V
• Parallel to V
• Parallel to V
• Parallel to V
TT
CCIO
at receiving end
/2 receiving end
internal bus is also connected to the internal V
, or parallel to
CCIO
CCIO
TT
CMT
/2
termination for differential inputs.
or GND
Zo
Zo
Zo
TT
Discrete Off-Chip Solution
is supported at the receiving end only. On-chip parallel output termination to V
VCCIO or GND
VCCIO2
OFF-chip
OFF-chip
OFF-chip
VTT
Zo
Zo
Zo
TT
is not available in all package styles.
TT
ON-chip
ON-chip
ON-chip
pins that must be connected if V
CMT
2-31
node. Thus in one bank designers can implement either
LatticeSC/M Family Data Sheet
Zo
Zo
Zo
Lattice On-Chip Solution
OFF-chip
OFF-chip
OFF-chip
TT
TT
is used. Note V
termination. The Thevenin
VCCIO or GND
2Zo
2Zo
Zo
Zo
ON-chip
ON-chip
ON-chip
VTT
VCCIO
GND
Architecture
TT
pins can
TT
TT
TT
is