LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 31

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 2-9. Supported Input Standards
Single Ended Interfaces
LVTTL33
LVCMOS 33, 25, 18, 15, 12
PCI33, PCIX33, AGP1X33
PCIX15
AGP2X33
HSTL18_I, II
HSTL18_III, IV
HSTL15_I, II
HSTL15_III, IV
SSTL33_I, II
SSTL25_I, II
SSTL18_I, II
GTL+, GTL
Differential Interfaces
SSTL18D_I, II
SSTL25D_I, II
SSTL33D_I, II
HSTL15D_I, II
HSTL18D_I, II
LVDS
Mini-LVDS
BLVDS25
MLVDS25
HYPT (Hyper Transport)
RSDS
LVPECL33
1. When not specified V
2. V
3. All ratioed input buffers and dedicated pin input buffers include hysteresis with a typical value of 50mV.
CCIO
Input Standard
3
needed for on-chip termination to V
CCIO
can be set anywhere in the valid operating range.
3
3
V
REF
1.0 / 0.8
0.75
1.32
1.08
0.75
1.25
0.9
0.9
1.5
0.9
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(Nom.)
CCIO
/2 or V
3.3/2.5/1.8/1.5/1.2 None
CCIO
V
CCIO
1.5 / 1.2
only. V
≤2.5
1.5
1.8
1.8
1.5
1.5
2.5
1.8
2.5
1.5
1.8
1.8
3.3
3.3
3.3
3.3
1
—
—
—
—
—
—
—
(Nom.)
2-27
2
2
2
2
2
2
2
2
2
2
CCIO
2
2
is not specified for off-chip termination or V
None
None
None / V
None
None / V
None / V
None / V
None / V
None
None / V
None / V
None / V
None / Diff: 120, 150, 220, 420/ Diff to V
220, 420 / V
None / Diff: 120, 150, 220, 420/ Diff to V
220, 420 / V
None
None / Diff: 120, 150, 220, 420/ Diff to V
220, 420 / V
None / Diff: 120, 150, 220, 420/ Diff to V
220, 420 / V
None / Diff: 120, 150, 220, 240/ Diff to V
220, 240
None / Diff: 120, 150 / Diff to V
None
None
None / Diff: 120, 150, 220, 240/ Diff to V
220, 240
None / Diff: 120, 150, 220, 240/ Diff to V
220, 240
None / Diff: 120, 150, 220, 240/ Diff to V
220, 240
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
LatticeSC/M Family Data Sheet
CCIO
CCIO
CCIO
CCIO
: 50
: 50
: 50
/ 2: 50, 60/ V
/ 2: 50, 60/ V
/ 2: 50, 60/ V
/ 2: 50, 60/ V
/ 2: 50, 60/ V
On-chip Termination
/ 2: 50, 60/ V
/ 2: 50, 60/ V
/ 2: 50, 60/ V
/ 2: 50, 60/ V
TT
TT
TT
TT
TT
: 60, 75, 120, 210
: 60, 75, 120, 210
: 60, 75, 120, 210
: 60, 75, 120, 210
: 60, 75, 120, 210
TT
TT
TT
TT
CMT
: 60, 75, 120, 210
: 60, 75, 120, 210
: 60, 75, 120, 210
: 60, 75, 120, 210
TT
: 120, 150
termination.
Architecture
CMT
CMT
CMT
CMT
CMT
CMT
CMT
CMT
: 120, 150,
: 120, 150,
: 120, 150,
: 120, 150,
: 120, 150,
: 120, 150,
: 120, 150,
: 120, 150,