LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 69

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
sysCLOCK PLL Timing
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
t
f
% Spread Percentage Downspread for SS Mode
1. Values are measured with FPGA logic active, no additional I/Os toggling and REFCLK total jitter = 30 ps
Parameter
IN
OUT
VCO
PFD
DT
OPJIT
CPJIT
SKEW
LOCK
IPJIT
HI
LO
RSWA
RSWD
DEL
RANGE
SS
1
1
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP,
CLKOS)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Output Clock Period Jitter
Output Clock Cycle-to-Cycle Jitter
Output Clock-to-Clock Skew (Between
Two Outputs with the Same Phase Set-
ting)
PLL Lock-in Time
Input Clock Period Jitter
Input Clock High Time
Input Clock Low Time
Analog Reset Signal Pulse Width
Digital Reset Signal Pulse Width
Timeshift Delay Step Size
Timeshift Delay Range
Spread Spectrum Modulation Frequency
VCO Clock Phase Adjustment Accuracy
Description
Over Recommended Operating Conditions
Default duty cycle selected
(at 50% levels)
2 MHz ≤ f
f
At 80% level
At 20% level
PFD
> 10 MHz
3-25
Conditions
PFD
≤ 10 MHz
DC and Switching Characteristics
LatticeSC/M Family Data Sheet
1.5625
Min.
100
350
350
100
0.5
45
40
30
—
—
—
—
—
—
—
-5
2
2
3
+/- 560
Typ
80
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Max.
1000
1000
1000
±250
700
200
100
100
120
500
1.5
55
20
—
—
—
—
—
1
5
Units
MHz
MHz
MHz
MHz
KHz
ms
ps
ps
ps
ps
ps
ps
ns
ns
ps
ps
%
ps
%
°