LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 40

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Since each quad has its own reference clock, different quads can support different standards on the same chip.
This feature makes the LatticeSC family of devices ideal for bridging between different standards.
flexiPCS quads are not dedicated solely to industry standard protocols. Each quad (and each channel within a
quad) can be programmed for many user defined data manipulation modes. For example, modes governing user-
defined word alignment and multi-channel alignment can be programmed for non-standard protocol applications.
For more information on the functions and use of the flexiPCS, refer to the LatticeSC flexiPCS Data Sheet.
System Bus
Each LatticeSC device connects the FPGA elements with a standardized bus framework referred to as a System
Bus. Multiple bus masters optimize system performance by sharing resources between different bus masters such
as the MPI and configuration logic. The wide data bus configuration of 32 bits with 4-bit parity supports high-band-
width, data intensive applications.
There are two types of interfaces on the System Bus, master and slave. A master interface has the ability to per-
form actions on the bus, such as writes and reads to and from a specific address. A slave interface responds to the
actions of a master by accepting data and address on a write and providing data on a read. The System Bus has a
memory map which describes each of the slave peripherals that is connected on the bus. Using the addresses
listed in the memory map, a master interface can access each of the slave peripherals on the System Bus. Any and
all peripherals on the System Bus can be used at the same time. Table 2-12 list all of the available user peripherals
on the System Bus after device power-up.
Table 2-12. System Bus User Peripherals
The peripherals listed in Table 2-12 can be added when the System Bus module is created using Module IP/Man-
ager (ispLEVER Module/IP Manager).
Figure 2-31 also lists the existing peripherals on the System Bus. The gray boxes are available only during configu-
ration. Refer to Lattice technical note TN1080, LatticeSC sysCONFIG Usage Guide, for configuration options. The
Status and Config box refers to internal System Bus registers. This document presents all the interfaces listed in
Table 2-12 in detail to help the user utilize the desired functions of the System Bus.
Micro Processor Interface
User Master Interface
User Slave Interface
Serial Management Interface (PLL, DLL, User Logic)
Physical Coding Sublayer
Direct FPGA Access
Peripheral
2-36
Name
PCS
UMI
DFA
MPI
SMI
USI
LatticeSC/M Family Data Sheet
Interface Type
Master
Master
Slave
Slave
Slave
Slave
Architecture