LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 33

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
PCI Clamp
A programmable PCI clamp is available on the top and bottom banks of the device. The PCI clamp can be turned
“ON” or “OFF” on each pin independently. The PCI clamp is used when implementing a 3.3V PCI interface. The PCI
Specification, Revision 2.2 requires the use of clamping diodes for 3.3V operation. For more information on the PCI
interface, please refer to the PCI Specification, Revision 2.2.
Programmable Slew Rate Control
All output and bidirectional buffers have an optional programmable output slew rate control that can be configured
for either low noise or high-speed performance. Each I/O pin has an individual slew rate control. This allows
designers to specify slew rate control on a pin-by-pin basis. This slew rate control affects both the rising and falling
edges.
Programmable Termination
Many of the I/O standards supported by the LatticeSC devices require termination at the transmitter, receiver or both.
The SC devices provide the capability to implement many kinds of termination on-chip, minimizing stub lengths and
hence improving performance. Utilizing this feature also has the benefit of reducing the number of discrete compo-
nents required on the circuit board. The termination schemes can be split into two categories single-ended and differ-
ential.
Single Ended Termination
Single Ended Outputs: The SC devices support a number of different terminations for single ended outputs:
Figure 2-27 shows the single ended output schemes that are supported. The nominal values of the termination resis-
tors are shown in Table 2-10.
• Series
• Parallel to V
• Parallel to V
• Parallel to V
CCIO
CCIO
CCIO
/2
/2 combined with series
or GND
2-29
LatticeSC/M Family Data Sheet
Architecture