LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 26

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the PURESPEED I/O buffers. The block contains a register for SDR operation and a group of
three registers for DDR and shift register operation. The output signal tri-state control signal (TO) can be derived
directly from one of the inputs (bypass mode), the SDR shift register, the DDR registers or the data associated with
the buffer (for open drain emulation). Figure 2-24 shows the diagram of the Tristate Register Block.
Tristate SDR Register/Latch Block
The SDR register operates on the positive edge of the high-speed clock. In it has a variety of programmable
options for set/reset including, set or reset, asynchronous or synchronous Local Set Reset LSR and Global Set
Reset GSR enable or disable. The register LSR input is driven from LSRO, which is generated from the PIO control
MUX. The GSR input is driven from the GSR output of the PIO control MUX, which allows the global set-reset to be
disabled on a PIO basis.
Tristate DDR/Shift Register Block
The DDR/Shift block is shared with the output block allowing DDR support using the high-speed clock and the
associated transfer from the low-speed clock domain. It functions as a gearbox allowing low–speed parallel data
from the FPGA fabric to provide a high-speed tri-state control stream.
There is a special mode for DDR-II memory interfaces where the termination is controlled by the output tristate sig-
nal. During WRITE cycle when the FPGA is driving the lines, the parallel terminations are turned off. During READ
cycle when the FPGA is receiving data, the parallel terminations are turned on.
Figure 2-24. Tristate Register Block
I/O Architecture Rules
Table 2-6 shows the PIO usage for x1, x2, x4 gearing. The checkmarks in the columns show the specific PIOs that
are used for each gearing mode. When using x2 or x4 gearing, any PIO which is not used for gearing can still be
used as an output.
Routing
Control
From
From
MUX
HCLKOUT
LCLKOUT
ONEG1
OPOS1
TD
Notes:
1. CE, Update, Set and Reset not shown for clarity.
2. DDR/Shift Register Block shared with output register block.
GND
VCC
1
DDR/Shift Register Block
•
• DDR + half clock
DDR
2-22
2
LatticeSC/M Family Data Sheet
From Output
(To PURESPEED
I/O Buffer)
TO
Architecture