LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 29

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-26. LatticeSC Banks
Table 2-7. Maximum Number of I/Os Per Bank in LatticeSC Family
The LatticeSC devices contain three types of PURESPEED I/O buffers:
1. Left and Right Sides (Banks 2, 3, 6 and 7)
2. Top Side (Bank 1)
These buffers can support LVCMOS standards up to 2.5V. A differential output driver (for LVDS, RSDS, and
HYPT) is provided on all primary PIO pairs (A and B) and differential receivers are available on all pairs. Com-
plimentary drivers are available. Adaptive input logic is available on PIOs A or C.
These buffers can support LVCMOS standards up to 3.3V, including PCI33, PCI-X33 and SSTL-33. Differential
receivers are provided on all PIO pairs but differential drivers for LVDS, RSDS, and HYPT are not available.
Adaptive input logic is not available on this side. Complimentary output drivers are available.
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Note: Not all the I/Os of the Banks are available in all the packages
Device
V
V
V
V
GND
V
V
V
V
GND
CCIO7
REF1[7]
TT7
REF2[7]
CCIO6
REF1[6]
TT6
REF2[6]
LFSC/M15
104
28
60
72
72
60
28
SERDES
Bank 5
LFSC/M25
100
100
80
36
84
84
36
Bank 1
2-25
LFSC/M40
Bank 4
136
124
124
60
96
96
60
SERDES
LatticeSC/M Family Data Sheet
LFSC/M80
132
184
184
132
80
96
96
V
V
V
V
GND
V
V
V
V
GND
CCIO2
REF1[2]
TT2
REF2[2]
CCIO3
REF1[3]
TT[3]
REF2[3]
LFSC/M115
136
136
156
208
208
156
136
Architecture