LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 76

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Signal Descriptions (Cont.)
Lattice Semiconductor
PROBE_GND
PLL and Clock Functions (Used as user-programmable I/O pins when not in use for PLL, DLL or clock pins.)
[LOC]_PLL[T, C]_FB_[A/B]
[LOC]_DLL[T, C]_FB_[C, D, E, F]
[LOC]_PLL[T, C]_IN[A/B]
[LOC]_DLL[T, C]_IN[C, D, E, F]
PCLKxy_z
Test and Programming (Dedicated pins. Pull-up is enabled on input pins during configuration.)
TMS
TCK
TDI
TDO
Configuration Pads (Dedicated pins. Used during sysCONFIG.)
M[3:0]
INITN
PROGRAMN
DONE
CCLK
Signal Name
I/O
I/O
I/O
I/O
—
O
I
I
I
I
I
I
I
I
GND signal - Connected to internal VSS node. Can be used for feed-
back to control an external board power converter. Can be uncon-
nected if not used.
PLL feedback input. Pull-ups are enabled on input pins during configu-
ration. [LOC] indicates the corner the PLL is located in: ULC (upper
left), URC (upper right), LLC (lower left) and LRC (lower right). [T, C]
indicates whether input is true or complement. [A, B] indicates PLL ref-
erence within the corner.
DLL feedback input. Pull-ups are enabled on input pins during configu-
ration. [LOC] indicates the corner the DLL is located in: ULC (upper
left), URC (upper right), LLC (lower left) and LRC (lower right). [T/C]
indicates whether input is true or complement. [C, D, E, F] indicates
DLL reference within a corner. Note: E and F are only available on the
lower corners.
PLL reference clock input. Pull-ups are enabled on input pins during
configuration. [LOC] indicates the corner the PLL is located in: ULC
(upper left corner), URC (upper right corner), LLC (lower left corner)
and LRC (lower right corner). [T, C] indicates whether input is true or
complement.[A, B] indicates PLL reference within the corner.
DLL reference clock inputs. Pull-ups are enabled on input pins during
configuration. [LOC] indicates the corner the DLL is located in: ULC
(upper left corner), URC (upper right corner), LLC (lower left corner)
and LRC (lower right corner). [T/C] indicates whether input is true or
complement. [C, D, E, F] indicates DLL reference within a corner.
Note: E and F are only available on the lower corners. PCKLxy_[0:3]
can drive primary clocks, edge clocks, and CLKDIVs. PCLKxy_[4:7]
can only drive edge clocks.
General clock inputs. x indicates whether T (true) or C (complement).
y indicates the I/O bank the clock is associated with. z indicates the
clock number within a bank.
Test Mode Select input, used to control the 1149.1 state machine.
Test Clock input pin, used to clock the 1149.1 state machine.
Test Data in pin, used to load data into device using 1149.1 state
machine. After power-up, this TAP port can be activated for configura-
tion by sending appropriate command. (Note: once a configuration
port is selected it is locked. Another configuration port cannot be
selected until the power-up sequence).
Output pin -Test Data out pin used to shift data out of device using
1149.1.
Mode pins used to specify configuration modes values latched on ris-
ing edge of INITN.
Open Drain pin - Indicates the FPGA is ready to be configured. During
configuration, a pull-up is enabled that will pull the I/O above 1.5V.
Initiates configuration sequence when asserted low. This pin always
has an active pull-up.
Open Drain pin - Indicates that the configuration sequence is com-
plete, and the startup sequence is in progress.
Configuration Clock for configuring an FPGA in sysCONFIG mode.
4-2
LatticeSC/M Family Data Sheet
Description
Pinout Information