SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 101
![IC UART W/FIFO 48-TSSOP](/photos/6/50/65054/568-48-tssop_sot480-1_sml.jpg)
SC28L201A1DGG,112
Manufacturer Part Number
SC28L201A1DGG,112
Description
IC UART W/FIFO 48-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L201A1DGG118.pdf
(110 pages)
Specifications of SC28L201A1DGG,112
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3293-5
935277824112
SC28L201A1DGG
935277824112
SC28L201A1DGG
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Philips Semiconductors
9397 750 13138
Product data sheet
Fig 14. Clock timing
C/T clock
X1/SCLK
C1 = C2
C1 and C2 should be chosen according to the crystal manufacturer’s specification.
C1 and C2 values will include any parasitic capacitance of the wiring and X1, X2 pins.
Package capacitance approximately 4 pF.
RxC
TxC
24 pF for C
parasitic capacitance
parasitic capacitance
Fig 15. Transmitter external clocks
Fig 16. Receiver external clock
L
t
t
3 pF
3 pF
CTC
t
= 13.5 pF. For the oscillator feedback loop, the capacitors C1 and C2 are in series.
CLK
t
RX
TX
C2
C1
(1 output)
(1 output)
(input)
RXD
TXD
TxC
RxC
TxC
14.7456 MHz
t
t
CTC
t
Rev. 01 — 31 October 2005
CLK
t
RX
TX
X1
X2
2 pF
4 pF
t
d(o)(TXD)
(1 or 16 clocks)
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
SC28L201
160 k
(typ.)
1 bit time
t
su(RXD-RXCH)(D)
t
TCS
CLK
resistor required
for TTL input
t
h(RXCH-RXD)(D)
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
V
CC
470
to UART circuit
SC28L201
002aab482
002aab483
X1/SCLK
X2
(must be left open)
002aab481
101 of 110
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