SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 58

• Manufacturer Part Number: SC28L201A1DGG,112
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,112

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3293-5; 935277824112; SC28L201A1DGG

Philips Semiconductors
9397 750 13138
Product data sheet
8.2.9 Interrupt Mask Register (IMR)
The programming of this register selects which bits in the ISR cause an interrupt output. If
a bit in the ISR is a ‘1’ and the corresponding bit in the IMR is a ‘1’, the interrupt source is
presented to the internal interrupt arbitration circuits, eventually resulting in the IRQN
output being asserted (LOW). If the corresponding bit in the IMR is a zero, the state of the
bit in the ISR has no affect on the IRQN output.
Table 26:
Bit
7
6
5
4
3
2
1
0
Symbol
IMR - Interrupt Mask Register (address 0x25) bit description
Description
I/O port change-of-state. COS enable.
Allows a change of state in the inputs equipped with input change detectors
to cause an interrupt.
Rx watchdog time-out. Fixed watchdog enable.
Controls the generation of an interrupt watchdog timer event, If set, a count
of 64 idle bit times in the receiver will begin interrupt arbitration.
Address recognition event. Address recognition enable.
Enables the generation of an interrupt in response to changes in the
Address Recognition circuitry of the Special Mode (multi-drop or Wake-up
mode).
Xon/Xoff event. Xon/Xoff enable.
Enables the generation of an interrupt in response to recognition of an
in-band flow control character.
C/T Ready. Counter/Timer Enable.
Enable the C/T interrupt when the C/T reaches 0 count.
Break Change Of State.
Enables the generation of an interrupt when a Break condition has been
detected by the channel receiver.
RxRDY interrupt. Receiver (Rx) Enable.
Enables the generation of an interrupt when servicing for the RxFIFO is
desired.
TxRDY interrupt. Transmitter (Tx) Enable.
Enables the generation of an interrupt when servicing for the TxFIFO is
desired.
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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