SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 2

• Manufacturer Part Number: SC28L201A1DGG,112
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,112

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3293-5; 935277824112; SC28L201A1DGG

Philips Semiconductors
2. Features
9397 750 13138
Product data sheet
Member of IMPACT family: 3.3 V or 5.0 V, 40 C to +85 C and 80xxx or 68000 bus
interface (I/M modes)
Bit-by-bit real time transmission error check for high data integrity systems
Full-duplex independent asynchronous receiver/transmitter
256 character FIFOs for receiver and transmitter
Powers up to 9600 baud, 8 bits, no parity, 1 stop bit, interrupt disabled, all I/O set to
input
Pin programming to 68000 or 80xxx bus interface
Three character recognition system, used as:
Programmable data format
16-bit programmable Counter/Timer
Programmable baud rate for receiver and transmitter selectable from:
Parity, framing, and overrun error detection
Line break detection and generation; false start bit detection
Programmable channel mode
Multifunction 13-bit I/O input port
Versatile arbitrating interrupt system
Maximum data transfer rates: 1 clock = 3 Mbit/s; 16 clock = 3.125 Mbit/s
General purpose character recognition
Xon/Xoff character recognition
Address recognition Wake-up (multi-drop or 9-bit) mode
System provides 4 levels of automation on a recognition event
5 to 8 data bits plus parity and 9-bit mode
Odd, even, no parity, or force parity
9
27 fixed rates: 50 Bd to 2.0 MBd (includes MIDI rate)
Other baud rates via external clocks and C/T
Programmable user-defined rates derived from a programmable Counter/Timer
External 1 or 16 clock
Normal (full-duplex)
Automatic echo
Local loopback
Remote loopback
Multi-drop mode (also called ‘Wake-up’ or ‘9-bit’)
Can serve as clock or control inputs
Change-of-state detection on eight inputs
Inputs have typically > 100 M pull-up resistors
Modem and DMA interface
Interrupt system totally supports single query polling
Output port can be configured to provide a total of up to six separate interrupt type
outputs that may be wire-ORed (switched to open-drain)
Each FIFO can be independently programmed for any of 256 interrupt levels
Watchdog timer for receiver
16
, 1, 1.5 or 2 stop bits
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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