SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 39

• Manufacturer Part Number: SC28L201A1DGG,112
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,112

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3293-5; 935277824112; SC28L201A1DGG

Philips Semiconductors
9397 750 13138
Product data sheet
8.1.2 Special Feature and Status Register (SFSR A and B)
8.1.3 Test and Revision Register (TRR)
Table 7:
Table 8:
Bit
7:4
3
2:1
0
Bit
7
6:0
Symbol
-
-
Symbol
TRR[7]
TRR[6:0]
SFSR - Special Feature and Status Register (address 0x45) bit description
TRR - Test and Revision Register (address 0x67) bit description
Rev. 01 — 31 October 2005
Description
reserved
Loopback error; status of loopback error check
A ‘1’ indicates a loopback error occurred, which will be entered for
interrupt arbitration.
It can be cleared by the processor by a write to this register with D[3]
equal to ‘1’.
Remote loopback error check
Certification of returned data as Valid. (This feature implies the
transmitted data is being returned by the remote receiver.)
Sets automatic checking of returned data. This mode stores transmitted
data and compares it to data returned from the remote receiver. It is used
where relative short delay times are available, up to two characters in
time. This mode will totally relieve the processor of this task where
certainty of transmission and reception is required. The transmitted data
is looped back by the remote station with a half-bit time delay. The local
transmitted data is internally sent to the local receiver for comparison. An
interrupt is generated in the case of an error (data mismatch, parity or
framing).
reserved
Description
Test 2 enable
Bypass divide-by-16 counter in all TxC and RxC.
Chip Revision code
Indicates the revision of the chip. Initial code will be ‘000 0000’. The
revision code bits [6:0] are hard-wired. The default setting of the test bits
is all zeros.
0 = no
1 = yes (read only)
00 = disabled
01 = enabled, RxC
10 = enabled, RxC
00 = the checking is disabled
01 = return data is clocked in on rise of TxC
10 = return data is clocked on of rise of TxCN
00 = reserved
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
TxC
TxCN
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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