SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 55
![IC UART W/FIFO 48-TSSOP](/photos/6/50/65054/568-48-tssop_sot480-1_sml.jpg)
SC28L201A1DGG,112
Manufacturer Part Number
SC28L201A1DGG,112
Description
IC UART W/FIFO 48-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L201A1DGG118.pdf
(110 pages)
Specifications of SC28L201A1DGG,112
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3293-5
935277824112
SC28L201A1DGG
935277824112
SC28L201A1DGG
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Philips Semiconductors
9397 750 13138
Product data sheet
Table 24:
Bit
2
1
0
Symbol
TxRDY
RxFULL
RxRDY
SR - Channel Status Register (address 0x01) bit description
Description
Transmitter Ready.
This bit, when set, indicates that the TxFIFO is ready to be loaded with at
least one more character. This bit is cleared when the TxFIFO is full or is
above its interrupt threshold level set in the MR registers or TxFIFO interrupt
Fill Level register (TxFIL). Characters loaded in the TxFIFO while the
transmitter is disabled will not be transmitted.
RxFIFO Full.
This bit is set when a character is transferred from the Receive Shift Register
to the receive FIFO, and the transfer causes the FIFO to become full, that is,
all 256 RxFIFO positions are occupied. It is reset when the CPU reads the
RxFIFO and that read leaves one or more empty byte position(s). If a
character is waiting in the receive shift register because the RxFIFO is full,
RxFULL is not reset until the second read of the RxFIFO since the waiting
character is immediately loaded to the RxFIFO.
Receiver Ready.
This bit indicates that a character has been received and is waiting in the
RxFIFO to be read by the CPU. It is set when the character is transferred
from the receive shift register to the RxFIFO and reset when the CPU reads
the RxFIFO, and no more characters are in the RxFIFO.
0 = no
1 = yes
0 = no
1 = yes
0 = no
1 = yes
Rev. 01 — 31 October 2005
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
…continued
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