SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 76
![IC UART W/FIFO 48-TSSOP](/photos/6/50/65054/568-48-tssop_sot480-1_sml.jpg)
SC28L201A1DGG,112
Manufacturer Part Number
SC28L201A1DGG,112
Description
IC UART W/FIFO 48-TSSOP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L201A1DGG118.pdf
(110 pages)
Specifications of SC28L201A1DGG,112
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
256 Byte
Voltage - Supply
3.3V, 5V
With Parallel Port
Yes
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3293-5
935277824112
SC28L201A1DGG
935277824112
SC28L201A1DGG
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Philips Semiconductors
9397 750 13138
Product data sheet
8.6.3 Input Port Change Register Upper Nibble, A (IPCRU)
This register may be read to determine the current logical level of the I/O pins and
examine the output of the change detectors assigned to each pin. If the change detection
is not enabled or if the pin is configured as an output, the associated change field will read
‘0’.
Table 63:
Bit
7
6
5
4
3
2
1
0
Symbol
IPCRU - Input Port Change Register Upper Nibble, A (address 0x13)
bit description
Description
I/O7A state. Reads the actual logic level at the pin.
I/O6A state. Reads the actual logic level at the pin.
I/O5A state. Reads the actual logic level at the pin.
I/O4A state. Reads the actual logic level at the pin.
Rev. 01 — 31 October 2005
I/O7A change.
I/O6A change.
I/O5A change.
I/O4A change.
0 = no change
1 = change
0 = no change
1 = change
0 = no change
1 = change
0 = no change
1 = change
1 = HIGH level
0 = LOW level
1 = HIGH level
0 = LOW level
1 = HIGH level
0 = LOW level
1 = HIGH level
0 = LOW level
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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