SC28L201A1DGG,112 NXP Semiconductors, SC28L201A1DGG,112 Datasheet - Page 109

• Manufacturer Part Number: SC28L201A1DGG,112
• Description: IC UART W/FIFO 48-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L201A1DGG,112

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 48-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3293-5; 935277824112; SC28L201A1DGG

Philips Semiconductors
23. Contents
1
2
3
4
5
5.1
5.2
6
6.1
6.1.1
6.1.2
6.1.2.1
6.1.2.2
6.1.2.3
6.1.2.4
6.1.3
6.1.4
6.1.5
6.1.6
6.1.7
6.1.8
6.1.9
6.1.10
6.1.11
7
7.1
7.1.1
7.1.2
7.2
7.2.1
7.2.2
7.2.3
7.2.3.1
7.2.4
7.3
7.3.1
7.3.2
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
9397 750 13138
Product data sheet
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information . . . . . . . . . . . . . . . . . . . . . . 6
Functional description . . . . . . . . . . . . . . . . . . . 9
Detailed descriptions. . . . . . . . . . . . . . . . . . . . 13
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
Brief description of functional blocks . . . . . . . . 9
Bus interface: the two basic modes of bus
interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Timing circuits. . . . . . . . . . . . . . . . . . . . . . . . . 10
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 10
Fixed rate Baud Rate Generator (BRG) . . . . . 10
Counter/Timer. . . . . . . . . . . . . . . . . . . . . . . . . 10
Programmable BRG (PBRG) . . . . . . . . . . . . . 10
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Transmitter and receiver . . . . . . . . . . . . . . . . . 11
Transmitter real time error check . . . . . . . . . . 11
FIFO structures. . . . . . . . . . . . . . . . . . . . . . . . 11
Intelligent interrupt arbitration . . . . . . . . . . . . . 11
Character and address recognition. . . . . . . . . 12
Flow control . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Test modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . 13
DACKN cycle (68000 mode). . . . . . . . . . . . . . 13
IACKN cycle, update CIR . . . . . . . . . . . . . . . . 14
Timing circuits. . . . . . . . . . . . . . . . . . . . . . . . . 15
Crystal oscillator . . . . . . . . . . . . . . . . . . . . . . . 15
Baud rage generator (BRG) . . . . . . . . . . . . . . 15
Counter/Timer. . . . . . . . . . . . . . . . . . . . . . . . . 15
Counter/Timer programming. . . . . . . . . . . . . . 15
Programmable Baud Rate Generators
(PBRG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Input characteristics of the I/O ports. . . . . . . . 17
Output port of the I/O ports. . . . . . . . . . . . . . . 17
UART operation . . . . . . . . . . . . . . . . . . . . . . . 18
Receiver and transmitter. . . . . . . . . . . . . . . . . 18
Transmitter status bits. . . . . . . . . . . . . . . . . . . 18
Transmission of ‘break’ . . . . . . . . . . . . . . . . . . 19
1x and 16x modes, transmitter . . . . . . . . . . . . 19
Transmitter FIFO. . . . . . . . . . . . . . . . . . . . . . . 19
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Receiver operation . . . . . . . . . . . . . . . . . . . . . 20
Rev. 01 — 31 October 2005
7.4.7.1
7.4.7.2
7.4.7.3
7.4.7.4
7.4.7.5
7.4.7.6
7.4.7.7
7.4.7.8
7.4.7.9
7.4.8
7.4.8.1
7.4.8.2
7.4.8.3
7.4.8.4
7.4.8.5
7.4.8.6
7.4.9
7.4.9.1
7.4.10
7.4.10.1
7.4.10.2
7.4.10.3
7.4.10.4
7.4.10.5
7.4.10.6
7.4.10.7
7.4.10.8
7.5
8
8.1
8.1.1
8.1.2
8.1.3
8.1.4
8.1.5
8.1.6
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
3.3 V, 5 V UART, 3.125 Mbit/s, with 256-byte FIFO
Register description and programming note 37
1x and 16x modes, receiver . . . . . . . . . . . . . . 21
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Receiver status bits . . . . . . . . . . . . . . . . . . . . 22
Receiver FIFO . . . . . . . . . . . . . . . . . . . . . . . . 23
RxFIFO status bits, status reporting modes. . 23
Wake-up mode . . . . . . . . . . . . . . . . . . . . . . . . 24
Receiver reset and disable. . . . . . . . . . . . . . . 26
Receiver watchdog timer . . . . . . . . . . . . . . . . 26
Receiver Time-out mode . . . . . . . . . . . . . . . . 27
Arbitrating interrupt structure . . . . . . . . . . . . . 27
Enabling and activating interrupt sources . . . 29
Setting interrupt priorities . . . . . . . . . . . . . . . . 29
Interrupt arbitration and IRQN generation . . . 30
IACKN cycle, update CIR . . . . . . . . . . . . . . . . 31
Global registers . . . . . . . . . . . . . . . . . . . . . . . 31
Polling (normal and using the CIR) . . . . . . . . 32
Character and address recognition (also used
for multi-drop, Xon/Xoff systems) . . . . . . . . . . 32
Character stripping. . . . . . . . . . . . . . . . . . . . . 33
Flow control (Xon/Xoff). . . . . . . . . . . . . . . . . . 33
Mode control . . . . . . . . . . . . . . . . . . . . . . . . . 33
Xon/Xoff characters . . . . . . . . . . . . . . . . . . . . 34
Host mode (least efficient) . . . . . . . . . . . . . . . 34
Auto-transmitter mode . . . . . . . . . . . . . . . . . . 34
Receiver mode . . . . . . . . . . . . . . . . . . . . . . . . 35
Auto-receive and transmit (most efficient) . . . 35
Xon/Xoff interrupts . . . . . . . . . . . . . . . . . . . . . 36
Multi-drop, Wake-up, or 9-bit mode . . . . . . . . 36
Programming the host interface . . . . . . . . . . . 36
Registers that control global properties of the
SC28L201 . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Global Configuration Control Register (GCCR) 37
Special Feature and Status Register (SFSR A
and B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Test and Revision Register (TRR) . . . . . . . . . 39
Scan Test Control Register (STCR) . . . . . . . . 40
System Enable Status register A and B (SES) 40
Enhanced Operation Status register (EOS) . . 41
UART registers . . . . . . . . . . . . . . . . . . . . . . . . 41
Mode Register 0 (MR0) . . . . . . . . . . . . . . . . . 42
Mode Register 1 (MR1) . . . . . . . . . . . . . . . . . 44
Mode Register 2 (MR2) . . . . . . . . . . . . . . . . . 46
Mode Register 3 (MR3) . . . . . . . . . . . . . . . . . 48
Receiver Clock Select Register (RxCSR) and
Transmitter Clock Select Register (TxCSR) . . 49
Command Register Extension (CRx) . . . . . . . 51
Channel Status Register (SR) . . . . . . . . . . . . 54
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC28L201
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