AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 191

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.6.4.6
Table 15-4.
15.6.4.7
32072G–11/2011
Coded Value
setup [5:0]
pulse [6:0]
cycle [8:0]
Coding timing parameters
Usage restriction
Coding and Range of Timing Parameters
Number of Bits
6
7
9
All timing parameters are defined for one chip select and are grouped together in one register
according to their type.
The Setup register (SETUP) groups the definition of all setup parameters:
The Pulse register (PULSE) groups the definition of all pulse parameters:
The Cycle register (CYCLE) groups the definition of all cycle parameters:
Table 15-4 on page 191
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP
and PULSE parameters is larger than the corresponding CYCLE parameter, this leads to unpre-
dictable behavior of the SMC.
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the
memory interface because of the propagation delay of theses signals through external logic and
pads. If positive setup and hold values must be verified, then it is strictly recommended to pro-
gram non-null values so as to cover possible skews between address, NCS and NRD signals.
For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address,
byte select lines, and NCS signal after the rising edge of NWE. This is true if the MODE.WRITE-
MODE bit is written to one. See
For read and write operations: a null value for pulse parameters is forbidden and may lead to
unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the
address bus. For external devices that require setup and hold time between NCS and NRD sig-
nals (read), or between NCS and NWE signals (write), these setup and hold times must be
converted into setup and hold times in reference to the address bus.
• NRDSETUP, NCSRDSETUP, NWESETUP, and NCSWRSETUP.
• NRDPULSE, NCSRDPULSE, NWEPULSE, and NCSWRPULSE.
• NRDCYCLE, NWECYCLE.
256 x cycle[8:7] + cycle[6:0]
128 x setup[5] + setup[4:0]
256 x pulse[6] + pulse[5:0]
Effective Value
shows how the timing parameters are coded and their permitted range.
Section
15.6.5.2.
128 ≤ value ≤ 255
256 ≤ value ≤ 383
384 ≤ value ≤ 511
64 ≤ value ≤ 127
32 ≤ value ≤ 63
0 ≤ value ≤ 127
0 ≤ value ≤ 31
0 ≤ value ≤ 63
Coded Value
Permitted Range
256 ≤ value ≤ 256+127
512 ≤ value ≤ 512+127
768 ≤ value ≤ 768+127
128 ≤ value ≤ 128+31
256 ≤ value ≤ 256+63
Effective Value
0 ≤ value ≤ 127
0 ≤ value ≤ 31
0 ≤ value ≤ 63
191