AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 251

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

AT32UC3A3/A4
For ECC-RS, in order to perform 4-error correction per 512 bytes of 8-bit words, the codeword
have to be generated by the RS4 Encoder module and stored into the NAND Flash extra area,
according to the scheme shown in
Figure 17-5 on page 251
Figure 17-5. RS Codeword Generation
Feedback
α
α
α
α
α
α
α
α
395
28
603
383
539
500
397
402
+
DataIn
+
+
+
+
+
+
+
CW7
CW6
CW5
CW4
CW3
CW2
CW1
CW0
In read mode, firstly, the detection for any error is done with the partial syndrome module. It is
the responsibility of the ECC-RS Controller to determine after receiving the old codeword stored
in the extra area if there is any error on data and /or on the old codeword. If all syndromes (Si)
are equal to zero, there is no error, otherwise a polynomial representation is written into
CWPS00 to CWPS79 registers. The Partial Syndrome module performs an algorithm according
to the scheme in
Figure 17-6 on page 251
Figure 17-6. Partial Syndrome Block Diagram
S7
Mult α
i
x
S2
x
S1
x
RegOct
S0
DataIn(x)
If the Correction Enable bit is set in the ECC Mode Register (MD.CORRS4) then the polynomial
representation of error are sent to the polynomial processor. The aim of this module is to per-
form the polynomial division in order to calculate two polynomials, Omega (Z) and Lambda (Z),
which are necessary for the two following modules (Chien Search and Error Evaluator). In order
to perform addition, multiplication, and division a Read Only Memory (ROM) has been added
containing the 1024 elements of the Galois field. Both Chien Search and Error Evaluator work in
parallel. The Error Evaluator has the responsibility to determine the Nth error value in the data
and in the old codeword according to the scheme in
Figure 17-7 on page 252
251
32072G–11/2011