AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 48

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.5.6.2
7.5.7
7.5.7.1
7.5.7.2
32072G–11/2011
Sleep Modes
Mask ready flag
Entering and exiting sleep modes
Supported sleep modes
Due to synchronization in the clock generator, there is a slight delay from a mask register is writ-
ten until the new mask setting goes into effect. When clearing mask bits, this delay can usually
be ignored. However, when setting mask bits, the registers in the corresponding module must
not be written until the clock has actually be re-enabled. The status flag MSKRDY in ISR pro-
vides the required mask status information. When writing either mask register with any value,
this bit is cleared. The bit is set when the clocks have been enabled and disabled according to
the new mask setting. Optionally, the Power Manager interrupt can be enabled by writing the
MSKRDY bit in IER.
In normal operation, all clock domains are active, allowing software execution and peripheral
operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other
clock domains to save power. This is activated by the sleep instruction, which takes the sleep
mode index number as argument.
The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains.
The modules will be halted regardless of the bit settings of the mask registers.
Oscillators and PLLs can also be switched off to save power. Some of these modules have a rel-
atively long start-up time, and are only switched off when very low power consumption is
required.
The CPU and affected modules are restarted when the sleep mode is exited. This occurs when
an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if
the source module is not clocked.
The following sleep modes are supported. These are detailed in
• Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any
• Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up
• Standby: All synchronous clocks are stopped, but oscillators and PLLs are running, allowing
• Stop: As Standby, but Oscillator 0 and 1, and the PLLs are stopped. 32 KHz (if enabled) and
• DeepStop: All synchronous clocks, Oscillator 0 and 1 and PLL 0 and 1 are stopped. 32 KHz
• Static: All oscillators, including 32 KHz and RC oscillator are stopped. Bandgap voltage
interrupt.
sources are any interrupt from PB modules.
quick wake-up to normal mode. Wake-up sources are RTC or external interrupt.
RC oscillators and RTC/WDT still operate. Wake-up sources are RTC, external interrupt, or
external reset pin.
oscillator can run if enabled. RC oscillator still operates. Bandgap voltage reference, BOD
and BOD33 are turned off. Wake-up sources are RTC, external interrupt (EIC) or external
reset pin.
reference, BOD and BOD33 detectors are turned off. Wake-up sources are external interrupt
(EIC) in asynchronous mode only or external reset pin.
Table 7-1 on page
49.
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