AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 286

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.7.3
Table 18-3.
18.7.4
Table 18-4.
Note:
32072G–11/2011
Offset
0x80C
0x81C
0x82C
Offset
0x800
0x804
0x808
0x810
0x814
0x818
0x820
0x824
0x828
0x830
0x834
1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
Performance Monitor Memory Map
Version Register Memory Map
PDCA Performance Monitor Registers
PDCA Version Register Memory Map
Note:
Performance Control Register
Channel0 Read Max Latency
Channel1 Read Max Latency
Channel0 Write Max Latency
Channel1 Write Max Latency
Channel0 Read Data Cycles
Channel0 Write Data Cycles
Channel1 Read Data Cycles
Channel1 Write Data Cycles
Channel0 Read Stall Cycles
Channel1 Read Stall Cycles
Channel0 Write Stall Cycles
Channel1 Write Stall Cycles
Version Register
1. The number of performance monitors is device specific. If the device has only one perfor-
Register
Register
mance monitor, the Channel1 registers are not available. Please refer to the Module
Configuration section at the end of this chapter for the number of performance monitors on this
device.
(1)
Register Name
Register Name
PCONTROL
PWSTALL0
PWSTALL1
PRSTALL0
PRSTALL1
PWDATA0
PWDATA1
PRDATA0
PRDATA1
VERSION
PWLAT0
PWLAT1
PRLAT0
PRLAT1
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Access
Access
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
Reset
-
(1)
286