AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 557

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.6.3.4
32072G–11/2011
Manchester Decoder
Figure 25-12. Asynchronous Character Reception
When MR.MAN is one, the Manchester endec is enabled. The decoder can detect selectable
preamble sequences and start frame delimiters. The Receiver Manchester Polarity bit
(MAN.RX_MPOL) selects input stream polarity. The Receiver Preamble Length field
(MAN.RX_PL) specifies the length characteristics of detectable preambles, and if written to zero
the preamble pattern detection will be disabled. The Receiver Preamble Pattern field
(MAN.RX_PP) selects the pattern to be detected. See
terns.
The Manchester endec uses the same Start Frame Delimiter Selector (MR.ONEBIT) for both
encoder and decoder. If ONEBIT is one, only a Manchester encoded zero will be accepted as a
valid start frame delimiter. If ONEBIT is zero, a data or command sync pattern will be expected.
The Received Sync bit in the Receive Holding Register (RHR.RXSYNH) will be zero if it is a data
sync, and a one if it is a command sync.
Figure 25-13. Preamble Pattern Mismatch
The receiver samples the RX line in continous bit period quarters, making the smallest time
frame in which to assume a bit value three quarters. A start bit is assumed if RXD is zero during
one of these quarters. See
Figure 25-14. Asynchronous Start Bit Detection
Baud Rate
Manchester
Example: 8-bit, Parity Enabled
Detection
Manchester
Figure 25-13
Sampling
encoded
encoded
Start
(16 x)
Clock
Clock
RXD
data
data
Txd
Txd
illustrates two types of Manchester preamble pattern mismatches.
samples
16
1
D0
Figure
Manchester coding error
samples
2
16
Preamble Mismatch
3
D1
25-14.
samples
Preamble Length is set to 8
4
16
Detection
D2
samples
Start
16
D3
samples
16
Preamble Mismatch
D4
samples
Figure 25-8
invalid pattern
16
D5
samples
16
D6
samples
for available preamble pat-
16
D7
samples
SFD
16
Parity
Bit
samples
16
DATA
Stop
Bit
557