AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 888

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 32-3. DMA Mode when MR.LOD is zero
Figure 32-4. DMA Mode when MR.LOD is one
Table 32-3.
Note:
Warning: In DMA mode, reading to the ODATAnR registers before the last data transfer may lead to unpredictable results.
32072G–11/2011
Encryption/Decryption
Encrypted/Decrypted
Data Result Location
Clearing Condition
ISR.DATRDY bit
1. Depending on the mode, there are other ways of clearing the DATRDY.ISR bit. See the Interrupt Status Register (ISR)
End of
definition.
Last Output Mode Behavior versus Start Modes
(1)
The user must first wait for the DMA Controller Interrupt, then for ISR.DATRDY to ensure that
the encryption/decryption is completed.
In this case, no receive buffers are required.
The output data is only available in ODATAnR registers.
Following table summarizes the different cases.
D M A C o n tro lle r In te rru p t
DMA Controller Interrupt
At least one ODATAnR
In ODATAnR registers
register must be read
• when MR.LOD is one
ISR.DATRDY
MR.LOD = 0
ISR.DATRDY
Manual and Automatic Modes
E n a b le D M A C o n tro lle r C h a n n e ls (R e ce ive a n d T ra n sm it C h a n n e ls )
Enable DMA Controller Channels (only Transmit Channel)
register must be written
In ODATAnR registers
At least one IDATAnR
Multiple Encryption or Decryption Processes
M u ltip le e n cryp tio n o r d e c ryp tio n p ro ce ss e s
ISR.DATRDY
MR.LOD = 1
DMA Controller
configuration of
DMA Controller
specified in the
At the address
MR.LOD = 0
Not used
Interrupt
DMA Mode
Managed by the
In ODATAnR registers
DMA Controller
Interrupt then
DATRDY.ISR
MR.LOD = 1
Controller
DMA
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