AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 408

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.7.3.1
Figure 21-5. Master Mode Block Diagram
32072G–11/2011
Master mode block diagram
CLK_SPI
In master mode, if the received data is not read fast enough compared to the transfer rhythm
imposed by the write accesses in the TDR, some overrun errors may occur, even if the FIFO is
enabled. To insure a perfect data integrity of received data (especially at high data rate), the
mode Wait Data Read Before Transfer can be enabled in the MR register (MR.WDRBT). When
this mode is activated, no transfer starts while received data remains unread in the RDR. When
data is written to the TDR and if unread received data is stored in the RDR, the transfer is
paused until the RDR is read. In this mode no overrun error can occur. Please note that if this
mode is enabled, it is useless to activate the FIFO in reception.
ure 21-6 on page 409
Figure 21-5 on page
NPCS0
MISO
MR
TDR
PCS
PCS
MSTR
CSR0..3
CSR0..3
PS
LSB
Baud Rate Generator
408shows a block diagram of the SPI when operating in master mode.
0
1
shows a flow chart describing how transfers are handled.
NCPHA
CPOL
BITS
SCBR
PCSDEC
CSR0..3
Clock
SPI
Shift Register
CSNAAT
CSAAT
TDR
RXFIFOEN
Peripheral
Current
RXFIFOEN
MODFDIS
TD
0
1
0
1
MSB
RDR
4 – Character FIFO
RDR
4 – Character FIFO
TDRE
MODF
RD
NPCS3
NPCS2
NPCS1
NPCS0
MOSI
SPCK
OVRES
RDRF
Fig-
408