AT32UC3A3128 Atmel Corporation, AT32UC3A3128 Datasheet - Page 212

• Manufacturer Part Number: AT32UC3A3128
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3128

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.7.1
Register Name:
Access Type:
Offset:
Reset Value:
• NCSRDSETUP: NCS Setup Length in READ Access
• NRDSETUP: NRD Setup Length
• NCSWRSETUP: NCS Setup Length in WRITE Access
• NWESETUP: NWE Setup Length
32072G–11/2011
31
23
15
–
–
–
7
–
In read access, the NCS signal setup length is defined as:
The NRD signal setup length is defined in clock cycles as:
In write access, the NCS signal setup length is defined as:
The NWE signal setup length is defined as:
Setup Register
NCS Setup Length in write access
NCS Setup Length in read access
30
22
14
6
–
–
–
–
SETUP
Read/Write
0x00 + CS_number*0x10
0x01010101
NWE Setup Length
NRD Setup Length
29
21
13
5
=
=
(
(
128 NWESETUP 5 [ ]
128 NRDSETUP 5 [ ] NRDSETUP 4:0
=
=
(
(
×
×
128 NCSWRSETUP 5 [ ]
128 NCSRDSETUP 5 [ ]
28
20
12
4
×
×
27
19
11
+
3
+
NCSWRSETUP
NCSRDSETUP
NWESETUP 4:0
NWESETUP
NRDSETUP
+
+
NCSRDSETUP 4:0
NCSWRSETUP 4:0
[
[
26
18
10
2
]
]
) clock cycles
) clock cycles
[
[
]
]
) clock cycles
) clock cycles
25
17
9
1
24
16
8
0
212