AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 167

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.6
14.6.1
14.6.2
14.6.3
14.6.4
32072G–11/2011
Functional Description
Bus Multiplexing
Static Memory Controller
SDRAM Controller
ECCHRS Controller
Table 14-3.
The EBI transfers data between the internal HSB bus (handled by the HMATRIX) and the exter-
nal memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control busses and is composed of the following elements:
The EBI offers a complete set of control signals that share the 16-bit data lines, the address
lines of up to 24 bits and the control signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output control lines at a stable state while no external access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAMC without delaying the
other external memory controller accesses.
For information on the Static Memory Controller, refer to the Static Memory Controller Section.
Writing a one to the HMATRIX.SFR6.CS1A bit enables the SDRAM logic.
For information on the SDRAM Controller, refer to the SDRAM Section.
For information on the ECCHRS Controller, refer to the ECCHRS Section.
• The Static Memory Controller (SMC)
• The SDRAM Controller (SDRAMC)
• The ECCHRS Controller (ECCHRS)
• A chip select assignment feature that assigns an HSB address space to the external devices
• A multiplex controller circuit that shares the pins between the different memory controllers
• Programmable CompactFlash support logic
• Programmable SmartMedia and NAND Flash support logic
SFR6 Bit
Number
2
1
0
EBI Special Function Register Fields Description
CS2A
CS1A
Bit name
0 = Chip Select 2 (NCS[2]) is connected to a Static Memory device. For each
access to the NCS[2] memory space, all related pins act as SMC pins
1 = Chip Select 2 (NCS[2]) is connected to a NandFlash or a SmartMedia
device. For each access to the NCS[2] memory space, all related pins act as
NandFlash or SmartMedia pins
0 = Chip Select 1 (NCS[1]) is connected to a Static Memory device. For each
access to the NCS[1] memory space, all related pins act as SMC pins
1 = Chip Select 1 (NCS[1]) is connected to a SDRAM device. For each access
to the NCS[1] memory space, all related pins act as SDRAM pins
Reserved
Description
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