AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 863

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

31. Memory Stick Interface (MSI)
31.1
31.2
Figure 31-1. Read packet
32072G–11/2011
Features
Overview
SDIO / DATA[3:0]
Rev: 2.1.0.0
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The Memory Stick Interface (MSI) is a host controller that supports Memory Stick Version 1.X
and Memory Stick PRO.
The communication protocol with the Memory Stick is started by write from the CPU to the com-
mand register. When the protocol finishes, the CPU is notified that the protocol has ended by an
interrupt request. When the protocol is started and enters the data transfer state, data is
requested by issuing a DMA transfer request (via DMACA) or an interrupt request to the CPU.
The RDY time out time when the handshake state (BS2 in read protocol, BS3 for write protocol)
is established in communication with the Memory Stick can be designated as the number of
Memory Stick transfer clocks. When a time out occurs, the CPU is notified that the protocol has
ended due to a time out error by an interrupt request.
CRC circuit can be set off for test mode purpose. When CRC is off, CRC is not added to the data
transmitted to the Memory Stick.
An interrupt request can also be issued to the CPU when a Memory Stick is inserted or removed.
Memory Stick ver. 1.x & Memory Stick PRO support
Memory Stick serial clock (serial mode: 20 MHz max., parallel mode: 40 MHz max.)
Data transmit/receive FIFO of 64 bits x 4
16 bits CRC circuit
DMACA transfer support
Card insertion/removal detection
SCLK
BS
Memory Stick
INT
BS0
BS1
Host
TPC
BS2
RDY/BSY
DATA
Memory Stick
BS3
CRC
BS0
INT
863