AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 247

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.5
17.5.1
17.5.2
32072G–11/2011
Functional Description
Write Access
Read Access
A page in NAND Flash and SmartMedia
tional area used for redundancy (ECC). The page is organized in 8-bit or 16-bit words. The page
size corresponds to the number of words in the main area plus the number of words in the extra
area used for redundancy.
Over time, some memory locations may fail to program or erase properly. In order to ensure that
data is stored properly over the life of the NAND Flash device, NAND Flash providers recom-
mend to utilize either one ECC per 256 bytes of data, one ECC per 512 bytes of data, or one
ECC for all of the page. For the next generation of deep micron SLC NAND Flash and with the
new MLC NAND Flash, it is also recommended to ensure at least a four-error ECC per 512
bytes whatever is the page size.
The only configurations required for ECC are the NAND Flash or the SmartMedia
(528/1056/2112/4224) and the type of correction wanted (one ECC-H for all the page, one ECC-
H per 256 bytes of data, one ECC-H per 512 bytes of data, or four-error ECC-RS per 512 bytes
of data). The page size is configured by writing in the Page Size field in the Mode Register
(MD.PAGESIZE). Type of correction is configured by writing the Type of Correction field in the
Mode Register (MD.TYPECORREC).
The ECC is automatically computed as soon as a read (0x00) or a write (0x80) command to the
NAND Flash or the SmartMedia
boundary.
The ECC results are available as soon as the counter reaches the end of the main area. The val-
ues in the Parity Registers (PR0 to PR15) for ECC-H and in the Codeword Parity registers
(CWPS00 to CWPS79) for ECC-RS are then valid and locked until a new start condition occurs
(read/write command followed by address cycles).
Once the Flash memory page is written, the computed ECC codes are available in PR0 to PR15
registers for ECC-H and in CWPS00 to CWPS79 registers for ECC-RS. The ECC code values
must be written by the software application in the extra area used for redundancy. The number
of write access in the extra area depends on the value of the MD.TYPECORREC field.
For example, for one ECC per 256 bytes of data for a page of 512 bytes, only the values of PR0
and PR1 must be written by the software application in the extra area. For ECC-RS, a NAND
Flash with page of 512 bytes, the software application will have to write the ten registers
CWPS00 to CWPS09 in the extra area, and would have to write 40 registers (CWPS00 to
CWPS39) for a NAND Flash with page of 2048 bytes.
Other registers are meaningless.
After reading the whole data in the main area, the application must perform read accesses to the
extra area where ECC code has been previously stored. Error detection is automatically per-
formed by the ECC-H controller or the ECC-RS controller. In ECC-RS, writing a one to the Halt
of Computation bit in the ECC Mode Register (MD.FREEZE) allows to stop error detection when
software is jumping to the correct parity area.
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is detected. Read and write access must start at a page
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memories contains an area for main data and an addi-
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page size
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