AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 807

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.6.1
Name:
Access Type:
Offset:
Reset Value:
• CHnRES: Channel Counter Reset
• CHnOF: Channel Overflow Freeze
• CHnEN: Channel Enabled
32072G–11/2011
31
23
15
7
-
-
-
-
Writting a one to this bit will reset the counter in the channel n.
Writting a zero to this bit has no effect.
This bit always reads as zero.
1: All channel n registers are frozen just before DATA or STALL overflows.
0: The channel n registers are reset if DATA or STALL overflows.
1: The channel n is enabled.
0: The channel n is disabled.
Control Register
30
22
14
6
-
-
-
-
CONTROL
Read/Write
0x00
0x00000000
29
21
13
5
-
-
-
-
28
20
12
4
-
-
-
-
CH3RES
CH3OF
CH3EN
27
19
11
3
-
CH2RES
CH2OF
CH2EN
26
18
10
2
-
CH1RES
CH1OF
CH1EN
25
17
9
1
-
CH0RES
CH0OF
CH0EN
24
16
8
0
-
807