AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 588

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.7.1
Name:
Access Type:
Offset:
Reset Value:
• LINWKUP: Send LIN Wakeup Signal
• LINABT: Abort LIN Transmission
• RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select
• RTSEN/FCS: Request to Send Enable/Force SPI Chip Select
• DTRDIS: Data Terminal Ready Disable
• DTREN: Data Terminal Ready Enable
• RETTO: Rearm Time-out
• RSTNACK: Reset Non Acknowledge
• RSTIT: Reset Iterations
32072G–11/2011
RETTO
TXDIS
31
23
15
–
–
7
Writing a zero to this bit has no effect.
Writing a one to this bit will sends a wakeup signal on the LIN bus.
Writing a zero to this bit has no effect.
Writing a one to this bit will abort the current LIN transmission.
Writing a zero to this bit has no effect.
Writing a one to this bit when USART is not in SPI master mode drives RTS pin high.
Writing a one to this bit when USART is in SPI master mode releases NSS (RTS pin).
Writing a zero to this bit has no effect.
Writing a one to this bit when USART is not in SPI master mode drives RTS low.
Writing a one to this bit when USART is in SPI master mode when;
FCS=0: has no effect.
FCS=1: forces NSS (RTS pin) low, even if USART is not transmitting, in order to address SPI slave devices supporting the
CSAAT Mode (Chip Select Active After Transfer).
Writing a zero to this bit has no effect.
Writing a one to this bit drives DTR pin high.
Writing a zero to this bit has no effect.
Writing a one to this bit drives DTR pin low.
Writing a zero to this bit has no effect.
Writing a one to this bit reloads the time-out counter and clears CSR.TIMEOUT.
Writing a zero to this bit has no effect.
Writing a one to this bit clears CSR.NACK.
Writing a zero to this bit has no effect.
Control Register
RSTNACK
TXEN
30
22
14
CR
Write-only
0x0
0x00000000
–
–
6
LINWKUP
RXDIS
RSTIT
29
21
13
–
5
LINABT
SENDA
RXEN
28
20
12
–
4
RTSDIS/RCS
STTTO
RSTTX
27
19
11
–
3
RTSEN/FCS
STPBRK
RSTRX
26
18
10
–
2
STTBRK
DTRDIS
25
17
–
9
1
–
RSTSTA
DTREN
24
16
–
8
0
–
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