AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 179

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.5.1
15.5.2
15.6
15.6.1
Figure 15-2. SMC Connections to Static Memory Devices
15.6.2
32072G–11/2011
Functional Description
I/O Lines
Clocks
Application Example
External Memory Mapping
Static Memory
Controller
NWR1/NBS1
NWR0/NWE
A0/NBS0
A2-A18
D0-D15
NCS0
NCS1
NCS2
NCS3
NCS4
NCS5
The SMC signals pass through the External Bus Interface (EBI) module where they are multi-
plexed. The user must first configure the I/O Controller to assign the EBI pins corresponding to
SMC signals to their peripheral function. If the I/O lines of the EBI corresponding to SMC signals
are not used by the application, they can be used for other purposes by the I/O Controller.
The clock for the SMC bus interface (CLK_SMC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
SMC before disabling the clock, to avoid freezing the SMC in an undefined state.
The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address
up to 16Mbytes of memory.
If the physical memory device connected on one chip select is smaller than 16Mbytes, it wraps
around and appears to be repeated within this space. The SMC correctly handles any valid
access to the memory device within the page (see
A[23:0] is only significant for 8-bit memory, A[23:1] is used for 16-bit memory23.
NWR0/NWE
NRD
D0-D7
CS
OE
WE
D0-D7
128K x 8
SRAM
A0-A16
A2-A18
Figure 15-3 on page
NWR1/NBS1
D8-D15
NRD
CS
OE
WE
D0-D7
128K x 8
SRAM
A0-A16
180).
A2-A18
179