AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 842

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

30.7.6
Name:
Access Type:
Offset:
Reset Value:
• BOOT_ACK: Boot Operation Acknowledge
• ATACS: ATA with Command Completion Signal
• IOSPCMD: SDIO Special Command
32072G–11/2011
IOSPCMD
31
23
15
7
-
-
-
This register is write-protected while SR.CMDRDY is zero. If an interrupt command is sent, this register is only writable by an
interrupt response (SPCMD field). This means that the current command execution cannot be interrupted or modified.
The master can choose to receive the boot acknowledge from the slave when a Boot Request command is isssued.
Writing a one to this bit indicates that a Boot acknolwedge is expected within a programmable amount of time defined with
DTOMUL and DTOCYC fields located in the DTOR register. If the acknowledge pattern is not received then an acknowledge
timeout error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern error is set.
Writing a one to this bit will configure ATA completion signal within a programmed amount of time in Completion Signal Time-out
Register (CSTOR).
Writing a zero to this bit will configure no ATA completion signal.
0
1
2
3
Command Register
RSPTYP
SDIO Special Command Type
Not a SDIO Special Command
SDIO Suspend Command
SDIO Resume Command
Reserved
30
22
14
6
-
-
-
CMDR
Write-only
0x014
0x00000000
29
21
13
5
-
-
MAXLAT
TRTYP
28
20
12
4
-
BOOTACK
OPDCMD
27
19
11
3
CMDNB
ATACS
TRDIR
26
18
10
2
SPCMD
25
17
9
1
IOSPCMD
TRCMD
24
16
8
0
842