AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 681

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

• SPDCONF: Speed Configuration
• RMWKUP: Remote Wake-Up
• DETACH: Detach
• ADDEN: Address Enable
• UADD: USB Address
32072G–11/2011
This field contains the peripheral speed.
Writing a one to this bit will send an upstream resume to the host for a remote wake-up.
Writing a zero to this bit has no effect.
This bit is cleared when the USBB receive a USB reset or once the upstream resume has been sent.
Writing a one to this bit will physically detach the device (disconnect internal pull-up resistor from D+ and D-).
Writing a zero to this bit will reconnect the device.
Writing a one to this bit will activate the UADD field (USB address).
Writing a zero to this bit has no effect.
This bit is cleared when a USB reset is received.
This field contains the device address.
This field is cleared when a USB reset is received.
0
0
1
1
SPDCONF
0
1
0
1
Speed
Normal mode: the peripheral starts in full-speed mode and performs a high-speed reset to
switch to the high-speed mode if the host is high-speed capable.
reserved, do not use this configuration
reserved, do not use this configuration
Full-speed: the peripheral remains in full-speed mode whatever is the host speed capability.
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