AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 705

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

26.8.2.18
Register Name:
Access Type:
Offset:
Reset Value:
• HSBADDR: HSB Address
32072G–11/2011
31
23
15
7
This field determines the HSB bus current address of a channel transfer.
The address written to the HSB address bus is HSBADDR rounded down to the nearest word-aligned address, i.e.,
HSBADDR[1:0] is considered as 0b00 since only word accesses are performed.
Channel HSB start and end addresses may be aligned on any byte boundary.
The user may write this field only when the Channel Enabled bit (CHEN) of the UDDMAnSTATUS register is cleared.
This field is updated at the end of the address phase of the current access to the HSB bus. It is incremented of the HSB access
byte-width.
The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written or loaded from the descriptor, whereas the channel end address is either determined by the
end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFFCLOSEINEN) is set.
Device DMA Channel n HSB Address Register
30
22
14
6
UDDMAnADDR, n in [1..7]
Read/Write
0x0314 + (n - 1) * 0x10
0x00000000
29
21
13
5
28
20
12
HSBADDR[31:24]
HSBADDR[23:16]
4
HSBADDR[15:8]
HSBADDR[7:0]
27
19
11
3
26
18
10
2
25
17
9
1
24
16
8
0
705