AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 246

• Manufacturer Part Number: AT32UC3A3256AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A3256AU

• Flash (kbytes): 256 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.3
17.4
17.4.1
17.4.2
17.4.3
17.4.4
32072G–11/2011
Block Diagram
Product Dependencies
I/O Lines
Power Management
Clocks
Interrupts
Figure 17-1. ECCHRS Block Diagram
In order to use this module, other parts of the system must be configured correctly, as described
below.
The ECCHRS signals pass through the External Bus Interface module (EBI) where they are
multiplexed.
The programmer must first configure the I/O Controller to assign the EBI pins corresponding to
the Static Memory Controller (SMC)
sponding to
the I/O Controller.
If the CPU enters a sleep mode that disables clocks used by the ECCHRS, the ECCHRS will
stop functioning and resume operation after the system wakes up from sleep mode.
The clock for the ECCHRS bus interface (CLK_ECCHRS) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the ECCHRS before disabling the clock, to avoid freezing the ECCHRS in an undefined
state.
The ECCHRS interrupt request line is connected to the interrupt controller. Using the ECCHRS
interrupt requires the interrupt controller to be programmed first.
NAND Flash
SmartMedia
Controller
Memory
Static
Logic
SMC
signals are not used by the application, they can be used for other purposes by
Partial Syndrome
Encoder RS4
Ctrl/ECC 1bit Algorithm
signals to their peripheral function. If I/O lines of the EBI corre-
HECC
Rom 1024x10
Peripheral Bus
Polynomial
GF(2 )
process
ECC Controller
10
User Interface
Error Evaluator
Chien Search
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