AT32UC3A3256AU Atmel Corporation, AT32UC3A3256AU Datasheet - Page 418
AT32UC3A3256AU
Manufacturer Part Number
AT32UC3A3256AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A0128AU.pdf
(2 pages)
5.AT32UC3A3128.pdf
(91 pages)
6.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3256AU
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128AU PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- AT32UC3A3128 PDF datasheet #6
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- Download datasheet (16Mb)
21.8.2
Name:
Access Type:
Offset:
Reset Value:
• DLYBCS: Delay Between Chip Selects
• PCS: Peripheral Chip Select
• LLB: Local Loopback Enable
• RXFIFOEN: FIFO in Reception Enable
32072G–11/2011
LLB
31
23
15
7
-
-
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-
overlapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six CLK_SPI periods will be inserted by default.
Otherwise, the following equation determines the delay:
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0NPCS[3:0] = 1110
PCS = xx01NPCS[3:0] = 1101
PCS = x011NPCS[3:0] = 1011
PCS = 0111NPCS[3:0] = 0111
PCS = 1111forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS.
1: Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in master mode only (MISO is
internally connected on MOSI).
0: Local loopback path disabled.
1: The FIFO is used in reception (four characters can be stored in the SPI).
Delay Between Chip Selects
Mode Register
RXFIFOEN
30
22
14
6
-
-
MR
Read/Write
0x04
0x00000000
WDRBT-
29
21
13
5
-
-
=
DLYBCS
---------------------- -
CLKSPI
MODFDIS
28
20
12
4
-
-
DLYBCS
27
19
11
3
-
-
PCSDEC
26
18
10
2
-
PCS
PS
25
17
9
1
-
MSTR
24
16
8
0
-
418
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