AT90USB1286 Atmel Corporation, AT90USB1286 Datasheet - Page 144

• Manufacturer Part Number: AT90USB1286
• Manufacturer: Atmel Corporation

Specifications of AT90USB1286

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 48
• Ext Interrupts: 16
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 10
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.10.5
14.10.6
14.10.7
144
AT90USB64/128
Timer/Counter1 Control Register C – TCCR1C
Timer/Counter3 Control Register C – TCCR3C
Timer/Counter1 – TCNT1H and TCNT1L
Table 14-5.
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
•
•
•
The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM
mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate compare
match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed
according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are imple-
mented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the
effect of the forced compare.
A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear
Timer on Compare Match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB/FOCnB bits are always read as zero.
•
These bits are reserved for future use. For ensuring compatibility with future devices, these bits
must be written to zero when TCCRnC is written.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
CSn2
Bit 7 – FOCnA: Force Output Compare for Channel A
Bit 6 – FOCnB: Force Output Compare for Channel B
Bit 5 – FOCnC: Force Output Compare for Channel C
Bit 4:0 – Reserved Bits
0
0
0
0
1
1
1
1
CSn1
0
0
1
1
0
0
1
1
7
FOC1A
W
0
7
FOC3A
W
0
7
Clock Select Bit Description
CSn0
6
FOC1B
W
0
6
FOC3B
W
0
6
0
1
0
1
0
1
0
1
Description
No clock source. (Timer/Counter stopped)
clk
clk
clk
clk
clk
External clock source on Tn pin. Clock on falling edge
External clock source on Tn pin. Clock on rising edge
5
FOC1C
W
0
5
FOC3C
W
0
5
I/O
I/O
I/O
I/O
I/O
/1 (No prescaling
/8 (From prescaler)
/64 (From prescaler)
/256 (From prescaler)
/1024 (From prescaler)
4
–
R
0
4
–
R
0
4
3
3
–
R
0
3
–
R
0
2
2
–
R
0
2
–
R
0
1
1
–
R
0
1
–
R
0
0
0
–
R
0
0
–
R
0
TCCR1C
TCCR3C
7593K–AVR–11/09