AT90USB1286 Atmel Corporation, AT90USB1286 Datasheet - Page 35

• Manufacturer Part Number: AT90USB1286
• Manufacturer: Atmel Corporation

Specifications of AT90USB1286

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 48
• Ext Interrupts: 16
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 10
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

5.5.7
7593K–AVR–11/09
External Memory Control Register B – XMCRB
Table 5-4.
• Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector
The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-
nal memory address space, see
• Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector
The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-
nal memory address space, see
Table 5-5.
Note:
• Bit 7– XMBK: External Memory Bus-keeper Enable
Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is
enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-
stated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE,
Bit
Read/Write
Initial Value
SRWn1
SRL2
0
0
1
1
0
0
0
1
1
1
1
1. n = 0 or 1 (lower/upper sector).
SRWn0
For further details of the timing and wait-states of the External Memory Interface, see Figures
5-6 through Figures 5-9 for how the setting of the SRW bits affects the timing.
7
XMBK
R/W
0
0
1
0
1
Sector limits with different settings of SRL2..0
Wait States
SRL1
0
1
1
0
0
1
1
R
6
–
0
Wait States
No wait-states
Wait one cycle during read/write strobe
Wait two cycles during read/write strobe
Wait two cycles during read/write and wait one cycle before driving out
new address
(1)
SRL0
5
–
R
0
x
0
1
0
1
0
1
Table
Table
4
–
R
0
Sector Limits
Lower sector = N/A
Upper sector = 0x2100 - 0xFFFF
Lower sector = 0x2100 - 0x3FFF
Upper sector = 0x4000 - 0xFFFF
Lower sector = 0x2100 - 0x5FFF
Upper sector = 0x6000 - 0xFFFF
Lower sector = 0x2100 - 0x7FFF
Upper sector = 0x8000 - 0xFFFF
Lower sector = 0x2100 - 0x9FFF
Upper sector = 0xA000 - 0xFFFF
Lower sector = 0x2100 - 0xBFFF
Upper sector = 0xC000 - 0xFFFF
Lower sector = 0x2100 - 0xDFFF
Upper sector = 0xE000 - 0xFFFF
5-5.
5-5.
3
–
R
0
2
XMM2
R/W
0
1
XMM1
R/W
0
AT90USB64/128
0
XMM0
R/W
0
XMCRB
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