AT90USB1286 Atmel Corporation, AT90USB1286 Datasheet - Page 457

• Manufacturer Part Number: AT90USB1286
• Manufacturer: Atmel Corporation

Specifications of AT90USB1286

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 48
• Ext Interrupts: 16
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 10
• Input Capture Channels: 1
• Pwm Channels: 9
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24 Analog Comparator .............................................................................. 310
25 Analog to Digital Converter - ADC ...................................................... 313
26 JTAG Interface and On-chip Debug System ...................................... 332
27 IEEE 1149.1 (JTAG) Boundary-scan ................................................... 338
7593K–AVR–11/09
23.9 Remote Wake-Up detection ..............................................................................293
23.10 USB Pipe Reset ...............................................................................................293
23.11 Pipe Data Access ............................................................................................293
23.12 Control Pipe management ...............................................................................294
23.13 OUT Pipe management ...................................................................................294
23.14 IN Pipe management .......................................................................................295
23.15 Interrupt system ...............................................................................................296
23.16 Registers .........................................................................................................297
24.1 Analog Comparator Multiplexed Input ...............................................................312
25.1 Features ............................................................................................................313
25.2 Operation ...........................................................................................................314
25.3 Starting a Conversion ........................................................................................315
25.4 Prescaling and Conversion Timing ....................................................................316
25.5 Changing Channel or Reference Selection .......................................................319
25.6 ADC Noise Canceler .........................................................................................320
25.7 ADC Conversion Result .....................................................................................324
25.8 ADC Register Description ..................................................................................326
26.1 Overview ............................................................................................................332
26.2 Test Access Port – TAP ....................................................................................332
26.3 TAP Controller ...................................................................................................334
26.4 Using the Boundary-scan Chain ........................................................................335
26.5 Using the On-chip Debug System .....................................................................335
26.6 On-chip Debug Specific JTAG Instructions .......................................................336
26.7 On-chip Debug Related Register in I/O Memory ...............................................337
26.8 Using the JTAG Programming Capabilities .......................................................337
26.9 Bibliography .......................................................................................................337
27.1 Features ............................................................................................................338
27.2 System Overview ...............................................................................................338
27.3 Data Registers ...................................................................................................338
27.4 Boundary-scan Specific JTAG Instructions .......................................................340
27.5 Boundary-scan Related Register in I/O Memory ...............................................341
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